[tblgen][CodeGenSchedule] Add a check for invalid RegisterFile definitions with zero...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344235 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp b/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp
index 0113125..4cfe1a5 100644 (file)
--- a/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp
+++ b/tools/llvm-mca/lib/HardwareUnits/RegisterFile.cpp
@@ -45,13 +45,11 @@ void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) {
   // object. The size of every register file, as well as the mapping between
   // register files and register classes is specified via tablegen.
   const MCExtraProcessorInfo &Info = SM.getExtraProcessorInfo();
-  for (unsigned I = 0, E = Info.NumRegisterFiles; I < E; ++I) {
+
+  // Skip invalid register file at index 0.
+  for (unsigned I = 1, E = Info.NumRegisterFiles; I < E; ++I) {
     const MCRegisterFileDesc &RF = Info.RegisterFiles[I];
-    // Skip invalid register files with zero physical registers.
-    // TODO: verify this constraint in SubtargetEmitter, and convert this
-    // statement into an assert.
-    if (!RF.NumPhysRegs)
-      continue;
+    assert(RF.NumPhysRegs && "Invalid PRF with zero physical registers!");
 
     // The cost of a register definition is equivalent to the number of
     // physical registers that are allocated at register renaming stage.

diff --git a/utils/TableGen/CodeGenSchedule.cpp b/utils/TableGen/CodeGenSchedule.cpp
index 881f1a8..f8d7d9a 100644 (file)
--- a/utils/TableGen/CodeGenSchedule.cpp
+++ b/utils/TableGen/CodeGenSchedule.cpp
@@ -1763,6 +1763,11 @@ void CodeGenSchedModels::collectRegisterFiles() {
     // Now set the number of physical registers as well as the cost of registers
     // in each register class.
     CGRF.NumPhysRegs = RF->getValueAsInt("NumPhysRegs");
+    if (!CGRF.NumPhysRegs) {
+      PrintFatalError(RF->getLoc(),
+                      "Invalid RegisterFile with zero physical registers");
+    }
+
     RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");
     std::vector<int64_t> RegisterCosts = RF->getValueAsListOfInts("RegCosts");
     for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) {