OSDN Git Service

ARM: dts: uniphier: add CPU clocks and OPP table for PXs2 SoC
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Wed, 26 Oct 2016 16:37:39 +0000 (01:37 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Sat, 5 Nov 2016 07:40:09 +0000 (16:40 +0900)
Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
arch/arm/boot/dts/uniphier-pxs2.dtsi

index 950f07b..83ba3e6 100644 (file)
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <0>;
+                       clocks = <&sys_clk 32>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       operating-points-v2 = <&cpu_opp>;
                };
 
                cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <1>;
+                       clocks = <&sys_clk 32>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       operating-points-v2 = <&cpu_opp>;
                };
 
                cpu@2 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <2>;
+                       clocks = <&sys_clk 32>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       operating-points-v2 = <&cpu_opp>;
                };
 
                cpu@3 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
                        reg = <3>;
+                       clocks = <&sys_clk 32>;
                        enable-method = "psci";
                        next-level-cache = <&l2>;
+                       operating-points-v2 = <&cpu_opp>;
+               };
+       };
+
+       cpu_opp: opp_table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp@100000000 {
+                       opp-hz = /bits/ 64 <100000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@150000000 {
+                       opp-hz = /bits/ 64 <150000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@300000000 {
+                       opp-hz = /bits/ 64 <300000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@600000000 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+                       clock-latency-ns = <300>;
+               };
+               opp@1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       clock-latency-ns = <300>;
                };
        };