.Default(false);
}
-static bool isSVEDataVectorRegister(StringRef Name) {
- return Name[0] == 'z';
-}
-
static void parseValidVectorKind(StringRef Name, unsigned &NumElements,
char &ElementKind) {
assert(isValidVectorKind(Name));
// Matches a register name or register alias previously defined by '.req'
unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
RegKind Kind) {
- unsigned RegNum;
- switch (Kind) {
- case RegKind::Scalar:
- RegNum = MatchRegisterName(Name);
- break;
- case RegKind::NeonVector:
- RegNum = MatchNeonVectorRegName(Name);
- break;
- case RegKind::SVEDataVector:
- RegNum = matchSVEDataVectorRegName(Name);
- break;
- }
+ unsigned RegNum = 0;
+ if ((RegNum = matchSVEDataVectorRegName(Name)))
+ return Kind == RegKind::SVEDataVector ? RegNum : 0;
+
+ if ((RegNum = MatchNeonVectorRegName(Name)))
+ return Kind == RegKind::NeonVector ? RegNum : 0;
+
+ // The parsed register must be of RegKind Scalar
+ if ((RegNum = MatchRegisterName(Name)))
+ return Kind == RegKind::Scalar ? RegNum : 0;
if (!RegNum) {
// Check for aliases registered via .req. Canonicalize to lower case.
return -1;
std::string lowerCase = Tok.getString().lower();
- if (isSVEDataVectorRegister(lowerCase))
- return -1;
-
unsigned RegNum = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
+
// Also handle a few aliases of registers.
if (RegNum == 0)
RegNum = StringSwitch<unsigned>(lowerCase)