[AArch64] Asm: Fix parsing of register aliases that have a name starting with 'z'

Summary: This fixes an issue as identified by @rnk in https://reviews.llvm.org/rL321029.

Reviewers: rnk, fhahn, rengolin, efriedma, echristo, olista01

Reviewed By: rnk, fhahn

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, rnk

Differential Revision: https://reviews.llvm.org/D41382

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321158 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index fd2ef18..83764aa 100644 (file)
--- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1936,10 +1936,6 @@ static bool isValidSVEKind(StringRef Name) {
       .Default(false);
 }
 
-static bool isSVEDataVectorRegister(StringRef Name) {
-  return Name[0] == 'z';
-}
-
 static void parseValidVectorKind(StringRef Name, unsigned &NumElements,
                                  char &ElementKind) {
   assert(isValidVectorKind(Name));
@@ -1969,18 +1965,16 @@ bool AArch64AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
 // Matches a register name or register alias previously defined by '.req'
 unsigned AArch64AsmParser::matchRegisterNameAlias(StringRef Name,
                                                   RegKind Kind) {
-  unsigned RegNum;
-  switch (Kind) {
-  case RegKind::Scalar:
-    RegNum = MatchRegisterName(Name);
-    break;
-  case RegKind::NeonVector:
-    RegNum = MatchNeonVectorRegName(Name);
-    break;
-  case RegKind::SVEDataVector:
-    RegNum = matchSVEDataVectorRegName(Name);
-    break;
-  }
+  unsigned RegNum = 0;
+  if ((RegNum = matchSVEDataVectorRegName(Name)))
+    return Kind == RegKind::SVEDataVector ? RegNum : 0;
+
+  if ((RegNum = MatchNeonVectorRegName(Name)))
+    return Kind == RegKind::NeonVector ? RegNum : 0;
+
+  // The parsed register must be of RegKind Scalar
+  if ((RegNum = MatchRegisterName(Name)))
+    return Kind == RegKind::Scalar ? RegNum : 0;
 
   if (!RegNum) {
     // Check for aliases registered via .req. Canonicalize to lower case.
@@ -2007,10 +2001,8 @@ int AArch64AsmParser::tryParseRegister() {
     return -1;
 
   std::string lowerCase = Tok.getString().lower();
-  if (isSVEDataVectorRegister(lowerCase))
-    return -1;
-
   unsigned RegNum = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
+
   // Also handle a few aliases of registers.
   if (RegNum == 0)
     RegNum = StringSwitch<unsigned>(lowerCase)

diff --git a/test/MC/AArch64/SVE/dot-req.s b/test/MC/AArch64/SVE/dot-req.s
new file mode 100644 (file)
index 0000000..c6816ea
--- /dev/null
+++ b/test/MC/AArch64/SVE/dot-req.s
@@ -0,0 +1,6 @@
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sve -show-encoding < %s 2>&1 | FileCheck %s
+
+foo:
+// CHECK: add z0.s, z1.s, z2.s
+  zbar .req z1
+  add  z0.s, zbar.s, z2.s

diff --git a/test/MC/AArch64/dot-req.s b/test/MC/AArch64/dot-req.s
index b2316be..582674b 100644 (file)
--- a/test/MC/AArch64/dot-req.s
+++ b/test/MC/AArch64/dot-req.s
@@ -42,3 +42,8 @@ bar:
        add peter, x0, x0
        .unreq peter
 // CHECK: add x6, x0, x0
+
+       zoe .req x6
+       add zoe, x0, x0
+       .unreq zoe
+// CHECK: add x6, x0, x0