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drm/amdgpu: remove explicit NULL init for parse_cs
authorChristian König <christian.koenig@amd.com>
Wed, 5 Oct 2016 12:23:00 +0000 (14:23 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Oct 2016 18:38:36 +0000 (14:38 -0400)
sed -i "/\.parse_cs = NULL,/d" drivers/gpu/drm/amd/amdgpu/*.c

That's just a leftover from radeon.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/cik_sdma.c
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/si_dma.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c

index cb952ac..34e4159 100644 (file)
@@ -1228,7 +1228,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
        .get_rptr = cik_sdma_ring_get_rptr,
        .get_wptr = cik_sdma_ring_get_wptr,
        .set_wptr = cik_sdma_ring_set_wptr,
-       .parse_cs = NULL,
        .emit_ib = cik_sdma_ring_emit_ib,
        .emit_fence = cik_sdma_ring_emit_fence,
        .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
index e3be5bd..4e35e16 100644 (file)
@@ -3258,7 +3258,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
        .get_rptr = gfx_v6_0_ring_get_rptr,
        .get_wptr = gfx_v6_0_ring_get_wptr,
        .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
-       .parse_cs = NULL,
        .emit_ib = gfx_v6_0_ring_emit_ib,
        .emit_fence = gfx_v6_0_ring_emit_fence,
        .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
@@ -3277,7 +3276,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
        .get_rptr = gfx_v6_0_ring_get_rptr,
        .get_wptr = gfx_v6_0_ring_get_wptr,
        .set_wptr = gfx_v6_0_ring_set_wptr_compute,
-       .parse_cs = NULL,
        .emit_ib = gfx_v6_0_ring_emit_ib,
        .emit_fence = gfx_v6_0_ring_emit_fence,
        .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
index e239e1d..9a54ea9 100644 (file)
@@ -5147,7 +5147,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
        .get_rptr = gfx_v7_0_ring_get_rptr,
        .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
        .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
-       .parse_cs = NULL,
        .emit_ib = gfx_v7_0_ring_emit_ib_gfx,
        .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
        .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
@@ -5168,7 +5167,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
        .get_rptr = gfx_v7_0_ring_get_rptr,
        .get_wptr = gfx_v7_0_ring_get_wptr_compute,
        .set_wptr = gfx_v7_0_ring_set_wptr_compute,
-       .parse_cs = NULL,
        .emit_ib = gfx_v7_0_ring_emit_ib_compute,
        .emit_fence = gfx_v7_0_ring_emit_fence_compute,
        .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync,
index bb17538..404c49c 100644 (file)
@@ -6568,7 +6568,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
        .get_rptr = gfx_v8_0_ring_get_rptr,
        .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
        .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
-       .parse_cs = NULL,
        .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
        .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
        .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
@@ -6590,7 +6589,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
        .get_rptr = gfx_v8_0_ring_get_rptr,
        .get_wptr = gfx_v8_0_ring_get_wptr_compute,
        .set_wptr = gfx_v8_0_ring_set_wptr_compute,
-       .parse_cs = NULL,
        .emit_ib = gfx_v8_0_ring_emit_ib_compute,
        .emit_fence = gfx_v8_0_ring_emit_fence_compute,
        .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync,
index 565dab3..16cc1f5 100644 (file)
@@ -1225,7 +1225,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
        .get_rptr = sdma_v2_4_ring_get_rptr,
        .get_wptr = sdma_v2_4_ring_get_wptr,
        .set_wptr = sdma_v2_4_ring_set_wptr,
-       .parse_cs = NULL,
        .emit_ib = sdma_v2_4_ring_emit_ib,
        .emit_fence = sdma_v2_4_ring_emit_fence,
        .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
index a9d1094..2c2f24f 100644 (file)
@@ -1568,7 +1568,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
        .get_rptr = sdma_v3_0_ring_get_rptr,
        .get_wptr = sdma_v3_0_ring_get_wptr,
        .set_wptr = sdma_v3_0_ring_set_wptr,
-       .parse_cs = NULL,
        .emit_ib = sdma_v3_0_ring_emit_ib,
        .emit_fence = sdma_v3_0_ring_emit_fence,
        .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
index de35819..9f11e37 100644 (file)
@@ -783,7 +783,6 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = {
        .get_rptr = si_dma_ring_get_rptr,
        .get_wptr = si_dma_ring_get_wptr,
        .set_wptr = si_dma_ring_set_wptr,
-       .parse_cs = NULL,
        .emit_ib = si_dma_ring_emit_ib,
        .emit_fence = si_dma_ring_emit_fence,
        .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync,
index ab3df6d..f742294 100644 (file)
@@ -1070,7 +1070,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
        .get_rptr = uvd_v6_0_ring_get_rptr,
        .get_wptr = uvd_v6_0_ring_get_wptr,
        .set_wptr = uvd_v6_0_ring_set_wptr,
-       .parse_cs = NULL,
        .emit_ib = uvd_v6_0_ring_emit_ib,
        .emit_fence = uvd_v6_0_ring_emit_fence,
        .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush,
index 8533269..e76bc09 100644 (file)
@@ -870,7 +870,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {
        .get_rptr = vce_v3_0_ring_get_rptr,
        .get_wptr = vce_v3_0_ring_get_wptr,
        .set_wptr = vce_v3_0_ring_set_wptr,
-       .parse_cs = NULL,
        .emit_ib = vce_v3_0_ring_emit_ib,
        .emit_vm_flush = vce_v3_0_emit_vm_flush,
        .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync,