--
entity de1_nes is
- port (\r
---debug signal\r
- signal dbg_cpu_clk : out std_logic;\r
- signal dbg_ppu_clk : out std_logic;\r
- signal dbg_mem_clk : out std_logic;\r
- signal dbg_r_nw : out std_logic;\r
- signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);\r
- signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);\r
- signal dbg_vram_ad : out std_logic_vector (7 downto 0);\r
- signal dbg_vram_a : out std_logic_vector (13 downto 8);\r
----monitor inside cpu\r
- signal dbg_instruction : out std_logic_vector(7 downto 0);\r
- signal dbg_int_d_bus : out std_logic_vector(7 downto 0);\r
- signal dbg_exec_cycle : out std_logic_vector (5 downto 0);\r
--- signal dbg_index_bus : out std_logic_vector(7 downto 0);\r
--- signal dbg_acc_bus : out std_logic_vector(7 downto 0);\r
- signal dbg_status : out std_logic_vector(7 downto 0);\r
- signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);\r
- signal dbg_dec_oe_n : out std_logic;\r
- signal dbg_dec_val : out std_logic_vector (7 downto 0);\r
- signal dbg_int_dbus : out std_logic_vector (7 downto 0);\r
--- signal dbg_status_val : out std_logic_vector (7 downto 0);\r
- signal dbg_stat_we_n : out std_logic;\r
-\r
---NES instance\r
+ port (
+--debug signal
+ signal dbg_cpu_clk : out std_logic;
+ signal dbg_ppu_clk : out std_logic;
+ signal dbg_mem_clk : out std_logic;
+ signal dbg_r_nw : out std_logic;
+ signal dbg_addr : out std_logic_vector( 16 - 1 downto 0);
+ signal dbg_d_io : out std_logic_vector( 8 - 1 downto 0);
+ signal dbg_vram_ad : out std_logic_vector (7 downto 0);
+ signal dbg_vram_a : out std_logic_vector (13 downto 8);
+---monitor inside cpu
+ signal dbg_instruction : out std_logic_vector(7 downto 0);
+ signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
+ signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
+-- signal dbg_index_bus : out std_logic_vector(7 downto 0);
+-- signal dbg_acc_bus : out std_logic_vector(7 downto 0);
+ signal dbg_status : out std_logic_vector(7 downto 0);
+ signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
+ signal dbg_dec_oe_n : out std_logic;
+ signal dbg_dec_val : out std_logic_vector (7 downto 0);
+ signal dbg_int_dbus : out std_logic_vector (7 downto 0);
+-- signal dbg_status_val : out std_logic_vector (7 downto 0);
+ signal dbg_stat_we_n : out std_logic;
+
+--NES instance
base_clk : in std_logic;
rst_n : in std_logic;
joypad1 : in std_logic_vector(7 downto 0);
generic ( dsize : integer := 8;
asize : integer :=16
);
- port ( \r
- signal dbg_instruction : out std_logic_vector(7 downto 0);\r
- signal dbg_int_d_bus : out std_logic_vector(7 downto 0);\r
- signal dbg_exec_cycle : out std_logic_vector (5 downto 0);\r
--- signal dbg_index_bus : out std_logic_vector(7 downto 0);\r
--- signal dbg_acc_bus : out std_logic_vector(7 downto 0);\r
- signal dbg_status : out std_logic_vector(7 downto 0);\r
- signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);\r
- signal dbg_dec_oe_n : out std_logic;\r
- signal dbg_dec_val : out std_logic_vector (7 downto 0);\r
- signal dbg_int_dbus : out std_logic_vector (7 downto 0);\r
--- signal dbg_status_val : out std_logic_vector (7 downto 0);\r
- signal dbg_stat_we_n : out std_logic;\r
-\r
+ port (
+ signal dbg_instruction : out std_logic_vector(7 downto 0);
+ signal dbg_int_d_bus : out std_logic_vector(7 downto 0);
+ signal dbg_exec_cycle : out std_logic_vector (5 downto 0);
+-- signal dbg_index_bus : out std_logic_vector(7 downto 0);
+-- signal dbg_acc_bus : out std_logic_vector(7 downto 0);
+ signal dbg_status : out std_logic_vector(7 downto 0);
+ signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : out std_logic_vector(7 downto 0);
+ signal dbg_dec_oe_n : out std_logic;
+ signal dbg_dec_val : out std_logic_vector (7 downto 0);
+ signal dbg_int_dbus : out std_logic_vector (7 downto 0);
+-- signal dbg_status_val : out std_logic_vector (7 downto 0);
+ signal dbg_stat_we_n : out std_logic;
+
input_clk : in std_logic; --phi0 input pin.
rdy : in std_logic;
rst_n : in std_logic;
reset_n : in std_logic;
cpu_clk : out std_logic;
ppu_clk : out std_logic;
- mem_clk : out std_logic;\r
+ mem_clk : out std_logic;
vga_clk : out std_logic
);
end component;
component address_decoder
generic (abus_size : integer := 16; dbus_size : integer := 8);
- port ( phi2 : in std_logic;\r
- mem_clk : in std_logic;\r
- R_nW : in std_logic; \r
- addr : in std_logic_vector (abus_size - 1 downto 0);\r
- d_io : in std_logic_vector (dbus_size - 1 downto 0);\r
- rom_ce_n : out std_logic;\r
- ram_ce_n : out std_logic;\r
- ppu_ce_n : out std_logic;\r
- apu_ce_n : out std_logic\r
+ port ( phi2 : in std_logic;
+ mem_clk : in std_logic;
+ R_nW : in std_logic;
+ addr : in std_logic_vector (abus_size - 1 downto 0);
+ d_io : in std_logic_vector (dbus_size - 1 downto 0);
+ rom_ce_n : out std_logic;
+ ram_ce_n : out std_logic;
+ ppu_ce_n : out std_logic;
+ apu_ce_n : out std_logic
);
end component;
- component ram\r
- generic (abus_size : integer := 16; dbus_size : integer := 8);\r
- port ( ce_n, oe_n, we_n : in std_logic; --select pin active low.\r
- addr : in std_logic_vector (abus_size - 1 downto 0);\r
- d_io : inout std_logic_vector (dbus_size - 1 downto 0)\r
- );\r
- end component;\r
-\r
- component prg_rom\r
- generic (abus_size : integer := 15; dbus_size : integer := 8);\r
- port (\r
- clk : in std_logic;\r
- ce_n : in std_logic; --active low.\r
- addr : in std_logic_vector (abus_size - 1 downto 0);\r
- data : out std_logic_vector (dbus_size - 1 downto 0)\r
- );\r
- end component;\r
-\r
+ component ram
+ generic (abus_size : integer := 16; dbus_size : integer := 8);
+ port (
+ clk : in std_logic;
+ ce_n, oe_n, we_n : in std_logic; --select pin active low.
+ addr : in std_logic_vector (abus_size - 1 downto 0);
+ d_io : inout std_logic_vector (dbus_size - 1 downto 0)
+ );
+ end component;
+
+ component prg_rom
+ generic (abus_size : integer := 15; dbus_size : integer := 8);
+ port (
+ clk : in std_logic;
+ ce_n : in std_logic; --active low.
+ addr : in std_logic_vector (abus_size - 1 downto 0);
+ data : out std_logic_vector (dbus_size - 1 downto 0)
+ );
+ end component;
+
component ppu
port ( clk : in std_logic;
+ mem_clk : in std_logic;
ce_n : in std_logic;
rst_n : in std_logic;
r_nw : in std_logic;
component chr_rom
generic (abus_size : integer := 13; dbus_size : integer := 8);
- port ( ce_n : in std_logic; --active low.
+ port (
+ clk : in std_logic;
+ ce_n : in std_logic; --active low.
addr : in std_logic_vector (abus_size - 1 downto 0);
data : out std_logic_vector (dbus_size - 1 downto 0);
nt_v_mirror : out std_logic
q : out std_logic_vector(dsize - 1 downto 0)
);
end component;
-\r
+
component apu
port ( clk : in std_logic;
ce_n : in std_logic;
constant addr_size : integer := 16;
constant vram_size14 : integer := 14;
- constant ram_2k : integer := 11; --2k = 11 bit width.\r
- constant rom_32k : integer := 15; --32k = 15 bit width.\r
- constant rom_4k : integer := 12; --4k = 12 bit width. (for test use)\r
+ constant ram_2k : integer := 11; --2k = 11 bit width.
+ constant rom_32k : integer := 15; --32k = 15 bit width.
+ constant rom_4k : integer := 12; --4k = 12 bit width. (for test use)
constant vram_1k : integer := 10; --1k = 10 bit width.
constant chr_rom_8k : integer := 13; --32k = 15 bit width.
-\r
+
signal cpu_clk : std_logic;
signal ppu_clk : std_logic;
- signal mem_clk : std_logic;\r
+ signal mem_clk : std_logic;
signal vga_out_clk : std_logic;
signal rdy, irq_n, nmi_n, dbe, r_nw : std_logic;
signal addr : std_logic_vector( addr_size - 1 downto 0);
signal d_io : std_logic_vector( data_size - 1 downto 0);
- signal rom_ce_n : std_logic;\r
- signal ram_ce_n : std_logic;\r
- signal ram_oe_n : std_logic;\r
+ signal rom_ce_n : std_logic;
+ signal ram_ce_n : std_logic;
+ signal ram_oe_n : std_logic;
signal ppu_ce_n : std_logic;
signal apu_ce_n : std_logic;
signal nt0_ce_n : std_logic;
signal nt1_ce_n : std_logic;
-\r
+
begin
irq_n <= '0';
--mos 6502 cpu instance
cpu_inst : mos6502 generic map (data_size, addr_size)
- port map (\r
- dbg_instruction,\r
- dbg_int_d_bus,\r
- dbg_exec_cycle,\r
- -- dbg_index_bus,\r
- -- dbg_acc_bus,\r
- dbg_status,\r
- dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc,\r
- dbg_dec_oe_n,\r
- dbg_dec_val,\r
- dbg_int_dbus,\r
--- dbg_status_val ,\r
- dbg_stat_we_n ,\r
-\r
- cpu_clk, '1', --rdy, -----for testing...\r
+ port map (
+ dbg_instruction,
+ dbg_int_d_bus,
+ dbg_exec_cycle,
+ -- dbg_index_bus,
+ -- dbg_acc_bus,
+ dbg_status,
+ dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc,
+ dbg_dec_oe_n,
+ dbg_dec_val,
+ dbg_int_dbus,
+-- dbg_status_val ,
+ dbg_stat_we_n ,
+
+ cpu_clk, '1', --rdy, -----for testing...
rst_n, irq_n, nmi_n, dbe, r_nw,
phi1, phi2, addr, d_io);
addr_dec_inst : address_decoder generic map (addr_size, data_size)
port map (phi2, mem_clk, r_nw, addr, d_io, rom_ce_n, ram_ce_n, ppu_ce_n, apu_ce_n);
-\r
- --main ROM/RAM instance\r
--- prg_rom_inst : prg_rom generic map (rom_32k, data_size)\r
--- port map (mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io);\r
- prg_rom_inst : prg_rom generic map (rom_4k, data_size)\r
- port map (mem_clk, rom_ce_n, addr(rom_4k - 1 downto 0), d_io);\r
-\r
- ram_oe_n <= not R_nW;\r
--- prg_ram_inst : ram generic map (ram_2k, data_size)\r
--- port map (ram_ce_n, ram_oe_n, R_nW, addr(ram_2k - 1 downto 0), d_io);\r
---\r
--- --nes ppu instance\r
--- ppu_inst : ppu \r
--- port map (ppu_clk, ppu_ce_n, rst_n, r_nw, addr(2 downto 0), d_io, \r
--- nmi_n, rd_n, wr_n, ale, vram_ad, vram_a,\r
--- vga_out_clk, h_sync_n, v_sync_n, r, g, b);\r
---\r
--- ppu_addr_decoder : v_address_decoder generic map (vram_size14, data_size) \r
--- port map (ppu_clk, rd_n, wr_n, ale, v_addr, vram_ad, \r
--- nt_v_mirror, pt_ce_n, nt0_ce_n, nt1_ce_n);\r
---\r
--- ---VRAM/CHR ROM instances\r
--- v_addr (13 downto 8) <= vram_a;\r
---\r
--- --transparent d-latch\r
--- vram_latch : ls373 generic map (data_size)\r
--- port map(ale, '0', vram_ad, v_addr(7 downto 0));\r
---\r
--- vchr_rom : chr_rom generic map (chr_rom_8k, data_size)\r
--- port map (pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad, nt_v_mirror);\r
---\r
--- --name table/attr table\r
--- vram_nt0 : ram generic map (vram_1k, data_size)\r
--- port map (nt0_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);\r
---\r
--- vram_nt1 : ram generic map (vram_1k, data_size)\r
--- port map (nt1_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);\r
---\r
--- --APU/DMA instance\r
--- apu_inst : apu\r
--- port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);\r
-\r
- dbg_cpu_clk <= cpu_clk;\r
- dbg_ppu_clk <= ppu_clk;\r
- dbg_mem_clk <= mem_clk;\r
- dbg_r_nw <= r_nw;\r
- dbg_addr <= addr;\r
- dbg_d_io <= d_io;\r
--- dbg_vram_ad <= vram_ad ;\r
--- dbg_vram_a <= vram_a ;\r
+
+ --main ROM/RAM instance
+-- prg_rom_inst : prg_rom generic map (rom_32k, data_size)
+-- port map (mem_clk, rom_ce_n, addr(rom_32k - 1 downto 0), d_io);
+ prg_rom_inst : prg_rom generic map (rom_4k, data_size)
+ port map (mem_clk, rom_ce_n, addr(rom_4k - 1 downto 0), d_io);
+
+ ram_oe_n <= not R_nW;
+-- prg_ram_inst : ram generic map (ram_2k, data_size)
+-- port map (mem_clk, ram_ce_n, ram_oe_n, R_nW, addr(ram_2k - 1 downto 0), d_io);
+--
+-- --nes ppu instance
+-- ppu_inst : ppu
+-- port map (ppu_clk, mem_clk, ppu_ce_n, rst_n, r_nw, addr(2 downto 0), d_io,
+-- nmi_n, rd_n, wr_n, ale, vram_ad, vram_a,
+-- vga_out_clk, h_sync_n, v_sync_n, r, g, b);
+--
+-- ppu_addr_decoder : v_address_decoder generic map (vram_size14, data_size)
+-- port map (ppu_clk, rd_n, wr_n, ale, v_addr, vram_ad,
+-- nt_v_mirror, pt_ce_n, nt0_ce_n, nt1_ce_n);
+--
+-- ---VRAM/CHR ROM instances
+-- v_addr (13 downto 8) <= vram_a;
+--
+-- --transparent d-latch
+-- vram_latch : ls373 generic map (data_size)
+-- port map(ale, '0', vram_ad, v_addr(7 downto 0));
+--
+-- vchr_rom : chr_rom generic map (chr_rom_8k, data_size)
+-- port map (mem_clk, pt_ce_n, v_addr(chr_rom_8k - 1 downto 0), vram_ad, nt_v_mirror);
+--
+-- --name table/attr table
+-- vram_nt0 : ram generic map (vram_1k, data_size)
+-- port map (mem_clk, nt0_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);
+--
+-- vram_nt1 : ram generic map (vram_1k, data_size)
+-- port map (mem_clk, nt1_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);
+--
+-- --APU/DMA instance
+-- apu_inst : apu
+-- port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);
+
+ dbg_cpu_clk <= cpu_clk;
+ dbg_ppu_clk <= ppu_clk;
+ dbg_mem_clk <= mem_clk;
+ dbg_r_nw <= r_nw;
+ dbg_addr <= addr;
+ dbg_d_io <= d_io;
+-- dbg_vram_ad <= vram_ad ;
+-- dbg_vram_a <= vram_a ;
end rtl;
----SRAM asyncronous memory.
entity ram is
generic (abus_size : integer := 16; dbus_size : integer := 8);
- port ( ce_n, oe_n, we_n : in std_logic; --select pin active low.
+ port (
+ clk : in std_logic;
+ ce_n, oe_n, we_n : in std_logic; --select pin active low.
addr : in std_logic_vector (abus_size - 1 downto 0);
d_io : inout std_logic_vector (dbus_size - 1 downto 0)
);
constant RAM_TOH : time := 10 ns; --write data hold time
begin
- p_write : process (ce_n, we_n)
+ p_write : process (clk)
begin
- if (ce_n = '0' and we_n = '0') then
- work_ram(conv_integer(addr)) <= d_io;
+ if (rising_edge(clk)) then
+ if (ce_n = '0' and we_n = '0') then
+ work_ram(conv_integer(addr)) <= d_io;
+ end if;
end if;
end process;
- p_read : process (ce_n, oe_n, addr)
+ p_read : process (clk)
begin
- if (ce_n= '0' and we_n = '1' and oe_n = '0') then
- d_io <= work_ram(conv_integer(addr));
- else
- d_io <= (others => 'Z');
+ if (rising_edge(clk)) then
+ if (ce_n= '0' and we_n = '1' and oe_n = '0') then
+ d_io <= work_ram(conv_integer(addr));
+ else
+ d_io <= (others => 'Z');
+ end if;
end if;
end process;
end rtl;
entity palette_ram is
generic (abus_size : integer := 16; dbus_size : integer := 8);
- port ( ce_n, oe_n, we_n : in std_logic; --select pin active low.
+ port (
+ clk : in std_logic;
+ ce_n, oe_n, we_n : in std_logic; --select pin active low.
addr : in std_logic_vector (abus_size - 1 downto 0);
d_io : inout std_logic_vector (dbus_size - 1 downto 0)
);
architecture rtl of palette_ram is
component ram
generic (abus_size : integer := 5; dbus_size : integer := 8);
- port ( ce_n, oe_n, we_n : in std_logic; --select pin active low.
+ port (
+ clk : in std_logic;
+ ce_n, oe_n, we_n : in std_logic; --select pin active low.
addr : in std_logic_vector (abus_size - 1 downto 0);
d_io : inout std_logic_vector (dbus_size - 1 downto 0)
);
plt_addr <= "0" & addr(3 downto 0) when addr (4) = '1' and addr (1) = '0' and addr (0) = '0' else
addr;
palette_ram_inst : ram generic map (abus_size, dbus_size)
- port map (ce_n, oe_n, we_n, plt_addr, d_io);
+ port map (clk, ce_n, oe_n, we_n, plt_addr, d_io);
+
+end rtl;
+
+-----------------------------------------------------
+-----------------------------------------------------
+--------------- ram timing adjuster -----------------
+-----------------------------------------------------
+-----------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ram_ctrl is
+ port (
+ clk : in std_logic;
+ ce_n, oe_n, we_n : in std_logic;
+ sync_ce_n : out std_logic
+ );
+end ram_ctrl;
+
+architecture rtl of ram_ctrl is
+component counter_register
+ generic (
+ dsize : integer := 8;
+ inc : integer := 1
+ );
+ port ( clk : in std_logic;
+ rst_n : in std_logic;
+ ce_n : in std_logic;
+ we_n : in std_logic;
+ d : in std_logic_vector(dsize - 1 downto 0);
+ q : out std_logic_vector(dsize - 1 downto 0)
+ );
+end component;
+
+signal cnt_rst_n : std_logic;
+signal clk_cnt : std_logic_vector(5 downto 0);
+
+begin
+
+ cnt_rst_n <= not ce_n;
+
+ counter_inst : counter_register generic map (6, 1)
+ port map (clk, cnt_rst_n, '0', '1', (others => '0'), clk_cnt);
+
+ sync_ce_n <= '0' when ce_n = '0' and oe_n = '0' and we_n = '1' else
+ '0' when ce_n = '0' and oe_n = '1' and we_n = '0' and clk_cnt = "000001" else
+ '1';
end rtl;
end motonesfpga_common;
+-------------------------------------------------------------
+-------------------------------------------------------------
+-------------------------------------------------------------
+------------------ other common modules ---------------------
+-------------------------------------------------------------
+-------------------------------------------------------------
+-------------------------------------------------------------
+
+----------------------------------------
+--- d-flipflop with set/reset
+----------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity d_flip_flop is
+ generic (
+ dsize : integer := 8
+ );
+ port (
+ clk : in std_logic;
+ res_n : in std_logic;
+ set_n : in std_logic;
+ we_n : in std_logic;
+ d : in std_logic_vector (dsize - 1 downto 0);
+ q : out std_logic_vector (dsize - 1 downto 0)
+ );
+end d_flip_flop;
+
+architecture rtl of d_flip_flop is
+begin
+
+ process (clk, res_n, set_n, d)
+ begin
+ if (res_n = '0') then
+ q <= (others => '0');
+ elsif (set_n = '0') then
+ q <= d;
+ elsif (clk'event and clk = '1') then
+ if (we_n = '0') then
+ q <= d;
+ end if;
+ end if;
+ end process;
+end rtl;
+
+
+--------- 1 bit d-flipflop.
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity d_flip_flop_bit is
+ port (
+ clk : in std_logic;
+ res_n : in std_logic;
+ set_n : in std_logic;
+ we_n : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+ );
+end d_flip_flop_bit;
+
+architecture rtl of d_flip_flop_bit is
+begin
+
+ process (clk, res_n, set_n, d)
+ begin
+ if (res_n = '0') then
+ q <= '0';
+ elsif (set_n = '0') then
+ q <= d;
+ elsif (clk'event and clk = '1') then
+ if (we_n = '0') then
+ q <= d;
+ end if;
+ end if;
+ end process;
+end rtl;
+
+----------------------------------------
+--- data latch declaration
+----------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity data_latch is
+ generic (
+ dsize : integer := 8
+ );
+ port (
+ clk : in std_logic;
+ d : in std_logic_vector (dsize - 1 downto 0);
+ q : out std_logic_vector (dsize - 1 downto 0)
+ );
+end data_latch;
+
+architecture rtl of data_latch is
+begin
+
+ process (clk, d)
+ begin
+ if ( clk = '1') then
+ --latch only when clock is high
+ q <= d;
+ end if;
+ end process;
+end rtl;
+
+----------------------------------------
+--- tri-state buffer
+----------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tri_state_buffer is
+ generic (
+ dsize : integer := 8
+ );
+ port (
+ oe_n : in std_logic;
+ d : in std_logic_vector (dsize - 1 downto 0);
+ q : out std_logic_vector (dsize - 1 downto 0)
+ );
+end tri_state_buffer;
+
+architecture rtl of tri_state_buffer is
+begin
+ q <= d when oe_n = '0' else
+ (others => 'Z');
+end rtl;
+
+-------------------------------
+------ count up registers -----
+-------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity counter_register is
+ generic (
+ dsize : integer := 8;
+ inc : integer := 1
+ );
+ port ( clk : in std_logic;
+ rst_n : in std_logic;
+ ce_n : in std_logic;
+ we_n : in std_logic;
+ d : in std_logic_vector(dsize - 1 downto 0);
+ q : out std_logic_vector(dsize - 1 downto 0)
+ );
+end counter_register;
+
+architecture rtl of counter_register is
+
+component d_flip_flop
+ generic (
+ dsize : integer := 8
+ );
+ port (
+ clk : in std_logic;
+ res_n : in std_logic;
+ set_n : in std_logic;
+ we_n : in std_logic;
+ d : in std_logic_vector (dsize - 1 downto 0);
+ q : out std_logic_vector (dsize - 1 downto 0)
+ );
+end component;
+
+use ieee.std_logic_unsigned.all;
+
+signal dff_we_n : std_logic;
+signal d_in : std_logic_vector(dsize - 1 downto 0);
+signal q_out : std_logic_vector(dsize - 1 downto 0);
+
+begin
+ q <= q_out;
+ dff_we_n <= ce_n and we_n;
+ counter_reg_inst : d_flip_flop generic map (dsize)
+ port map (clk, rst_n, '1', dff_we_n, d_in, q_out);
+
+ clk_p : process (clk, we_n, ce_n, d)
+ begin
+ if (we_n = '0') then
+ d_in <= d;
+ elsif (ce_n = '0') then
+ d_in <= q_out + inc;
+ end if;
+ end process;
+
+end rtl;
+
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