}
}
// set the field related to shift operations (except rrx).
- if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
- if(IsShiftByRegister) {
+ if (ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) {
+ if (IsShiftByRegister) {
// set the value of bit[11:8] (register Rs).
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
op = ARM_AM::getSORegOffset(MO2.getImm());
Value |= op << 7;
}
+ }
break;
}
default: assert(false && "Unknown operand type!");
if ((V & (Scale - 1)) != 0)
return false;
V /= Scale;
- return V == V & ((1LL << 5) - 1);
+ return V == (V & ((1LL << 5) - 1));
}
if (V < 0)
case MVT::i8:
case MVT::i32:
// +- imm12
- return V == V & ((1LL << 12) - 1);
+ return V == (V & ((1LL << 12) - 1));
case MVT::i16:
// +- imm8
- return V == V & ((1LL << 8) - 1);
+ return V == (V & ((1LL << 8) - 1));
case MVT::f32:
case MVT::f64:
if (!Subtarget->hasVFP2())
if ((V & 3) != 0)
return false;
V >>= 2;
- return V == V & ((1LL << 8) - 1);
+ return V == (V & ((1LL << 8) - 1));
}
}
if (AFI->getGPRCalleeSavedArea2Size() ||
AFI->getDPRCalleeSavedAreaSize() ||
AFI->getDPRCalleeSavedAreaOffset()||
- hasFP(MF))
+ hasFP(MF)) {
if (NumBytes)
BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
.addImm(NumBytes)
else
BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
.addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
+ }
} else if (NumBytes) {
emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this);
}
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
- assert(MBBI->getOpcode() == Alpha::RETDAG ||
- MBBI->getOpcode() == Alpha::RETDAGp
+ assert((MBBI->getOpcode() == Alpha::RETDAG ||
+ MBBI->getOpcode() == Alpha::RETDAGp)
&& "Can only insert epilog into returning blocks");
bool FP = hasFP(MF);
HasImplicitAddress = false; // HIA is only true if we haven't addressed yet
}
- assert(!HasImplicitAddress || (CI && CI->isNullValue()) &&
+ assert((!HasImplicitAddress || (CI && CI->isNullValue())) &&
"Can only have implicit address with direct accessing");
if (HasImplicitAddress) {
#include "llvm/Target/TargetRegisterInfo.h"
#include "IA64GenRegisterInfo.h.inc"
-namespace llvm { class llvm::Type; }
-
namespace llvm {
class TargetInstrInfo;
}
bool RetVoid = (F->getReturnType()->getTypeID() == Type::VoidTyID);
- if (BadSig || !F->getReturnType()->isInteger() && !RetVoid) {
+ if (BadSig || (!F->getReturnType()->isInteger() && !RetVoid)) {
Out << "\tldc.i4.0\n";
} else {
Out << "\tcall\t" << getTypeName(F->getReturnType()) <<
bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
if (LD->getValueType(0) != MVT::i64) {
// Handle PPC32 integer and normal FP loads.
- assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT) {
default: assert(0 && "Invalid PPC load type!");
case MVT::f64: Opcode = PPC::LFDU; break;
}
} else {
assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
- assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
switch (LoadedVT) {
default: assert(0 && "Invalid PPC load type!");
case MVT::i64: Opcode = PPC::LDU; break;
FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
- if (getRelocationModel() == Reloc::Default)
+ if (getRelocationModel() == Reloc::Default) {
if (Subtarget.isDarwin())
setRelocationModel(Reloc::DynamicNoPIC);
else
setRelocationModel(Reloc::Static);
+ }
}
/// Override this for PowerPC. Tail merging happily breaks up instruction issue
CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
- if (Subtarget->is64Bit())
+ if (Subtarget->is64Bit()) {
if (CC == CallingConv::Fast && PerformTailCallOpt)
return CC_X86_64_TailCall;
else
return CC_X86_64_C;
-
+ }
+
if (CC == CallingConv::X86_FastCall)
return CC_X86_32_FastCall;
else if (CC == CallingConv::Fast && PerformTailCallOpt)
default: assert(false && "Unexpected!");
}
- if (NewWidth == 2)
+ if (NewWidth == 2) {
if (MVT::isInteger(VT))
NewVT = MVT::v2i64;
else
NewVT = MVT::v2f64;
+ }
unsigned Scale = NumElems / NewWidth;
SmallVector<SDOperand, 8> MaskVec;
for (unsigned i = 0; i < NumElems; i += Scale) {
} else {
int DispVal = DispSpec.getImm();
if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
- if (NeedPlus)
+ if (NeedPlus) {
if (DispVal > 0)
O << " + ";
else {
O << " - ";
DispVal = -DispVal;
}
+ }
O << DispVal;
}
}
bool isDirectCall) const
{
// FIXME: PIC
- if (TM.getRelocationModel() != Reloc::Static)
+ if (TM.getRelocationModel() != Reloc::Static) {
if (isTargetDarwin()) {
return (!isDirectCall &&
(GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
} else if (isTargetCygMing() || isTargetWindows()) {
return (GV->hasDLLImportLinkage());
}
+ }
return false;
}
Subtarget.getStackAlignment(), Subtarget.is64Bit() ? -8 : -4),
InstrInfo(*this), JITInfo(*this), TLInfo(*this) {
DefRelocModel = getRelocationModel();
- if (getRelocationModel() == Reloc::Default)
+ if (getRelocationModel() == Reloc::Default) {
if (Subtarget.isTargetDarwin() || Subtarget.isTargetCygMing())
setRelocationModel(Reloc::DynamicNoPIC);
else
setRelocationModel(Reloc::Static);
+ }
if (Subtarget.is64Bit()) {
// No DynamicNoPIC support under X86-64.
if (getRelocationModel() == Reloc::DynamicNoPIC)
if (Subtarget.isTargetCygMing())
Subtarget.setPICStyle(PICStyle::WinPIC);
- else if (Subtarget.isTargetDarwin())
+ else if (Subtarget.isTargetDarwin()) {
if (Subtarget.is64Bit())
Subtarget.setPICStyle(PICStyle::RIPRel);
else
Subtarget.setPICStyle(PICStyle::Stub);
- else if (Subtarget.isTargetELF())
+ } else if (Subtarget.isTargetELF()) {
if (Subtarget.is64Bit())
Subtarget.setPICStyle(PICStyle::RIPRel);
else
Subtarget.setPICStyle(PICStyle::GOT);
+ }
}
//===----------------------------------------------------------------------===//