IB/mlx5: Add DCT RoCE LAG support

When DCT QPs work in RoCE LAG mode:
 1. DCT creation is allowed only when it is supported
 2. The "port" of a DCT QP is assigned in a round-robin way

Link: https://lore.kernel.org/r/20200818115245.700581-3-leon@kernel.org
Signed-off-by: Mark Zhang <markz@mellanox.com>
Reviewed-by: Maor Gottlieb <maorg@mellanox.com>
Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>

diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c
index 214d401..e51df89 100644 (file)
--- a/drivers/infiniband/hw/mlx5/qp.c
+++ b/drivers/infiniband/hw/mlx5/qp.c
@@ -2409,6 +2409,9 @@ static int create_dct(struct mlx5_ib_dev *dev, struct ib_pd *pd,
        u32 uidx = params->uidx;
        void *dctc;
 
+       if (mlx5_lag_is_active(dev->mdev) && !MLX5_CAP_GEN(dev->mdev, lag_dct))
+               return -EOPNOTSUPP;
+
        qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
        if (!qp->dct.in)
                return -ENOMEM;
@@ -4183,7 +4186,11 @@ static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
                        MLX5_SET(dctc, dctc, rae, 1);
                }
                MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
-               MLX5_SET(dctc, dctc, port, attr->port_num);
+               if (mlx5_lag_is_active(dev->mdev))
+                       MLX5_SET(dctc, dctc, port,
+                                get_tx_affinity_rr(dev, udata));
+               else
+                       MLX5_SET(dctc, dctc, port, attr->port_num);
 
                set_id = mlx5_ib_get_counters_id(dev, attr->port_num - 1);
                MLX5_SET(dctc, dctc, counter_set_id, set_id);

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index de1ffb4..aee25e4 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1430,7 +1430,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 
        u8         log_bf_reg_size[0x5];
 
-       u8         reserved_at_270[0x8];
+       u8         reserved_at_270[0x6];
+       u8         lag_dct[0x2];
        u8         lag_tx_port_affinity[0x1];
        u8         reserved_at_279[0x2];
        u8         lag_master[0x1];