Parameterize opcode encoding bits for Thumb2 extended precision integer

multiply instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121301 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 139dde1..5a36797 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -398,17 +398,21 @@ class T2FourReg<dag oops, dag iops, InstrItinClass itin,
   let Inst{3-0}   = Rm;
 }
 
-class T2MulLong<dag oops, dag iops, InstrItinClass itin,
-           string opc, string asm, list<dag> pattern>
+class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
+                dag oops, dag iops, InstrItinClass itin,
+                string opc, string asm, list<dag> pattern>
   : T2I<oops, iops, itin, opc, asm, pattern> {
   bits<4> RdLo;
   bits<4> RdHi;
   bits<4> Rn;
   bits<4> Rm;
 
+  let Inst{31-23} = 0b111110111;
+  let Inst{22-20} = opc22_20;
   let Inst{19-16} = Rn;
   let Inst{15-12} = RdLo;
   let Inst{11-8}  = RdHi;
+  let Inst{7-4}   = opc7_4;
   let Inst{3-0}   = Rm;
 }
 
@@ -2206,54 +2210,32 @@ def t2MLS: T2FourReg<
 // Extra precision multiplies with low / high results
 let neverHasSideEffects = 1 in {
 let isCommutable = 1 in {
-def t2SMULL : T2MulLong<
+def t2SMULL : T2MulLong<0b000, 0b0000,
                   (outs rGPR:$Rd, rGPR:$Ra),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
-                   "smull", "\t$Rd, $Ra, $Rn, $Rm", []> {
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b000;
-  let Inst{7-4} = 0b0000;
-}
+                   "smull", "\t$Rd, $Ra, $Rn, $Rm", []>;
 
-def t2UMULL : T2MulLong<
+def t2UMULL : T2MulLong<0b010, 0b0000,
                   (outs rGPR:$RdLo, rGPR:$RdHi),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
-                   "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []> {
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b010;
-  let Inst{7-4} = 0b0000;
-}
+                   "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 } // isCommutable
 
 // Multiply + accumulate
-def t2SMLAL : T2MulLong<(outs rGPR:$RdLo, rGPR:$RdHi),
+def t2SMLAL : T2MulLong<0b100, 0b0000,
+                  (outs rGPR:$RdLo, rGPR:$RdHi),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
-                  "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>{
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b100;
-  let Inst{7-4} = 0b0000;
-}
+                  "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 
-def t2UMLAL : T2MulLong<(outs rGPR:$RdLo, rGPR:$RdHi),
+def t2UMLAL : T2MulLong<0b110, 0b0000,
+                  (outs rGPR:$RdLo, rGPR:$RdHi),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
-                  "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>{
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b110;
-  let Inst{7-4} = 0b0000;
-}
+                  "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 
-def t2UMAAL : T2MulLong<(outs rGPR:$RdLo, rGPR:$RdHi),
+def t2UMAAL : T2MulLong<0b110, 0b0110,
+                  (outs rGPR:$RdLo, rGPR:$RdHi),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
-                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>{
-  let Inst{31-27} = 0b11111;
-  let Inst{26-23} = 0b0111;
-  let Inst{22-20} = 0b110;
-  let Inst{7-4} = 0b0110;
-}
+                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
 } // neverHasSideEffects
 
 // Rounding variants of the below included for disassembly only