ppu work env update

diff --git a/de1_nes/ppu/ppu.vhd b/de1_nes/ppu/ppu.vhd
index 20e15a4..953b1c2 100644 (file)
--- a/de1_nes/ppu/ppu.vhd
+++ b/de1_nes/ppu/ppu.vhd
@@ -32,7 +32,6 @@ entity ppu is
             ppu_clk     : in std_logic;
             vga_clk     : in std_logic;
             emu_ppu_clk : in std_logic;
-            mem_clk     : in std_logic;
             ce_n        : in std_logic;
             rst_n       : in std_logic;
             r_nw        : in std_logic;
@@ -77,7 +76,6 @@ component vga_ppu_render
 
             vga_clk     : in std_logic;
             emu_ppu_clk : in std_logic;
-            mem_clk     : in std_logic;
             rst_n       : in std_logic;
 
             --vram i/f
@@ -249,7 +247,7 @@ begin
     dbg_s_oam_addr                  ,
     dbg_s_oam_data                  ,
     
-            vga_clk, emu_ppu_clk, mem_clk, rst_n,
+            vga_clk, emu_ppu_clk, rst_n,
             rd_n, wr_n, ale, vram_ad, vram_a,
             h_sync_n, v_sync_n, r, g, b, 
             ppu_ctrl, ppu_mask, read_status, ppu_status, ppu_scroll_x, ppu_scroll_y,

diff --git a/de1_nes/ppu/vga_ppu.vhd b/de1_nes/ppu/vga_ppu.vhd
index d90421b..42b4e9b 100644 (file)
--- a/de1_nes/ppu/vga_ppu.vhd
+++ b/de1_nes/ppu/vga_ppu.vhd
@@ -32,7 +32,6 @@ entity vga_ppu_render is
 \r
             vga_clk     : in std_logic;\r
             emu_ppu_clk : in std_logic;\r
-            mem_clk     : in std_logic;\r
             rst_n       : in std_logic;\r
 \r
             --vram i/f\r
@@ -616,7 +615,7 @@ begin
     plt_d_buf_r : tri_state_buffer generic map (dsize)\r
             port map (plt_r_n, plt_data, oam_plt_data);\r
     palette_inst : palette_ram generic map (5, dsize)\r
-            port map (mem_clk, plt_ram_ce_n, plt_r_n, plt_w_n, plt_addr, plt_data);\r
+            port map (emu_ppu_clk, plt_ram_ce_n, plt_r_n, plt_w_n, plt_addr, plt_data);\r
 \r
 \r
     -----------------------------------------\r
@@ -652,7 +651,7 @@ begin
             port map (p_oam_r_n, p_oam_data, oam_plt_data);\r
 \r
     primary_oam_inst : ram generic map (dsize, dsize)\r
-            port map (mem_clk, p_oam_ram_ce_n, p_oam_r_n, p_oam_w_n, p_oam_addr, p_oam_data);\r
+            port map (emu_ppu_clk, p_oam_ram_ce_n, p_oam_r_n, p_oam_w_n, p_oam_addr, p_oam_data);\r
 \r
     -----------------------------------------\r
     ---secondary oam implementation\r
@@ -684,7 +683,7 @@ begin
                       '1';\r
 \r
     secondary_oam_inst : ram generic map (5, dsize)\r
-            port map (mem_clk, s_oam_ram_ce_n, s_oam_r_n, s_oam_w_n, s_oam_addr, s_oam_data);\r
+            port map (emu_ppu_clk, s_oam_ram_ce_n, s_oam_r_n, s_oam_w_n, s_oam_addr, s_oam_data);\r
 \r
     --sprite y tmp val\r
     spr_y_inst : d_flip_flop generic map(dsize)\r

diff --git a/de1_nes/simulation/modelsim/de1_nes_cmp_msim_rtl_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_cmp_msim_rtl_vhdl.do
index e1b4253..5ff1df4 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_cmp_msim_rtl_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_cmp_msim_rtl_vhdl.do
@@ -14,11 +14,11 @@ vcom -93 -work work {../../mem/ram.vhd}
 vcom -93 -work work {../../apu/apu.vhd}\r
 \r
 #ppu block...\r
-#vcom -93 -work work {../../mem/chr_rom.vhd}\r
-#vcom -93 -work work {../../ppu/ppu.vhd}\r
-#vcom -93 -work work {../../ppu/ppu_registers.vhd}\r
-#vcom -93 -work work {../../ppu/vga_ppu.vhd}\r
-vcom -93 -work work {../../dummy-ppu.vhd}\r
+vcom -93 -work work {../../mem/chr_rom.vhd}\r
+vcom -93 -work work {../../ppu/ppu.vhd}\r
+vcom -93 -work work {../../ppu/ppu_registers.vhd}\r
+vcom -93 -work work {../../ppu/vga_ppu.vhd}\r
+#vcom -93 -work work {../../dummy-ppu.vhd}\r
 \r
 #cpu block...\r
 vcom -93 -work work {../../mem/prg_rom.vhd}\r

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
index e781b43..6164d05 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
@@ -10,86 +10,59 @@ add wave -label addr -radix hex sim:/testbench_motones_sim/sim_board/addr
 add wave -label d_io -radix hex sim:/testbench_motones_sim/sim_board/d_io\r
 \r
 add wave -label instruction -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/instruction\r
-add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus\r
-add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle\r
-add wave -label ea_carry -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/dec_inst/ea_carry\r
-\r
-add wave -divider regs\r
-add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q\r
-add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val\r
-add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q\r
-add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q\r
-add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q\r
-\r
-add wave -label pcl -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pcl_inst/q\r
-add wave -label pch -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pch_inst/q\r
-add wave -label idl_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/idl_l/q\r
-\r
-\r
-#add wave -divider ppu\r
-#add wave  -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
-#add wave  -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
-#add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
-##add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
-##add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
-#add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
-#add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
-#add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
-##add wave -label ppu_addr_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_cnt\r
-##add wave -label ppu_addr_we_n -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_we_n\r
-##add wave -label ppu_addr_in -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_in\r
-##add wave -label ppu_addr_inc1 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc1\r
-##add wave -label ppu_addr_inc32 -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr_inc32\r
-#add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
-#add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
-#\r
-#\r
-#add wave -divider ppu_scrl\r
-##add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
-##add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk\r
-##add wave -label ppu_scroll_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt\r
-##add wave -label ppu_clk_cnt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_clk_cnt\r
-##\r
-##add wave -label ppu_scroll_cnt_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_cnt_ce_n\r
-##add wave -label ppu_scroll_x_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x_we_n\r
-##add wave -label ppu_scroll_y_we_n sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y_we_n\r
-#add wave -label ppu_scr_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x\r
-#add wave -label ppu_scr_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y\r
-#\r
-#\r
-#add wave -divider render\r
-##add wave -label vba_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_x\r
-#add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_x\r
-##add wave -label vga_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_y\r
-#add wave -label nes_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_y\r
-#\r
-#add wave -label ale sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ale\r
-#add wave -label rd_n sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/rd_n\r
-#add wave -label wr_n sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/wr_n\r
-\r
-#add wave -label cur_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/cur_x\r
-#add wave -label prf_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/prf_x\r
-#add wave -label cur_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/cur_y\r
-#add wave -label prf_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/prf_y\r
+#add wave -label int_d_bus -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/int_d_bus\r
+#add wave -label exec_cycle -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/exec_cycle\r
+#add wave -label ea_carry -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/dec_inst/ea_carry\r
+\r
+#add wave -divider cpu_regs\r
+#add wave -label acc -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/acc/q\r
+#add wave -label status_val -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_register/status_val\r
+#add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q\r
+#add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q\r
+#add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q\r
 #\r
+#add wave -label pcl -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pcl_inst/q\r
+#add wave -label pch -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pch_inst/q\r
+#add wave -label idl_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/idl_l/q\r
+\r
+\r
+add wave -divider ppu\r
+add wave -label cpu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_addr\r
+add wave -label cpu_d -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/cpu_d\r
+add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/ppu_inst/ce_n\r
+add wave -label ppu_ctl -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_ctrl\r
+add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_mask\r
+add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_status\r
+add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_addr\r
+add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_data\r
+add wave -label ppu_scr_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_x\r
+add wave -label ppu_scr_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/ppu_scroll_y\r
+\r
+\r
+add wave -divider render\r
+#add wave -label vba_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_x\r
+add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_x\r
+#add wave -label vga_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_y\r
+add wave -label nes_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_y\r
+\r
+add wave -label ale sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ale\r
+add wave -label rd_n sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/rd_n\r
+add wave -label wr_n sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/wr_n\r
+\r
 #add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_nt\r
 #add wave -label disp_attr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_attr\r
 #add wave -label attr_val -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/attr_val\r
 \r
 \r
-#add wave -divider vga\r
-#add wave -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/nes_r \\r
-#sim:/testbench_motones_sim/sim_board/ppu_inst/nes_g \\r
-#sim:/testbench_motones_sim/sim_board/ppu_inst/nes_b\r
-\r
-#add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n\r
-#add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n\r
+add wave -divider vga\r
+add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/h_sync_n\r
+add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/ppu_inst/v_sync_n\r
+add wave -label r -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/r\r
+add wave -label g -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/g\r
+add wave -label b -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/b\r
 \r
 \r
 \r
-#add wave -divider apu\r
-#add wave  -radix hex  sim:/testbench_motones_sim/sim_board/apu_inst/*\r
-\r
 #add wave -divider\r
 #add wave -radix hex  sim:/testbench_motones_sim/sim_board/clock_inst/*\r
 #add wave -divider\r
@@ -99,13 +72,16 @@ add wave -label idl_l -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/i
 #add wave -divider\r
 #add wave -radix hex  sim:/testbench_motones_sim/sim_board/cpu_inst/alu_inst/*\r
 \r
+#add wave -divider apu\r
+#add wave  -radix hex  sim:/testbench_motones_sim/sim_board/apu_inst/*\r
+\r
 \r
 view structure\r
 view signals\r
 \r
-run 8 us\r
+run 30 us\r
 wave zoom full\r
-run 890 us\r
+run 100 us\r
 #run 10000 us\r
 \r
 \r

diff --git a/de1_nes/simulation/modelsim/motones_modelsim.mpf b/de1_nes/simulation/modelsim/motones_modelsim.mpf
index e7e1e49..6dc37d9 100644 (file)
--- a/de1_nes/simulation/modelsim/motones_modelsim.mpf
+++ b/de1_nes/simulation/modelsim/motones_modelsim.mpf
@@ -127,7 +127,7 @@ cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
 hardcopyiv_hssi_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_hssi\r
 hardcopyiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/hardcopyiv_pcie_hip\r
 \r
-work = gate_work\r
+work = rtl_work\r
 [vcom]\r
 ; VHDL93 variable selects language version as the default. \r
 ; Default is VHDL-2002.\r