db/*\r
incremental_db/*\r
no-need/*\r
+output_files/*\r
simulation/*\r
greybox_tmp/*\r
undo_redo.txt\r
reset_n : in std_logic;
cpu_clk : out std_logic;
ppu_clk : out std_logic;
+ mem_clk : out std_logic;
vga_clk : out std_logic
);
end clock_divider;
architecture rtl of clock_divider is
-signal loop2 : std_logic_vector (0 downto 0);
-signal loop6 : std_logic_vector (2 downto 0);
+signal loop8 : std_logic_vector (2 downto 0);
+signal loop24 : std_logic_vector (4 downto 0);
signal base_clk_n : std_logic;
signal cpu_cnt_rst_n : std_logic;
signal cpu_we_n : std_logic;
end component;
begin
+ --Actual NES base clock = 21.477272 MHz
+ --CPU clock = base clock / 12
+ --PPU clock = base clock / 4
+ --Actual NES CPU clock = 1.78 MHz (559 ns / cycle)
+ --VGA clock = 25 MHz.
+
+
+ ---DE1 base clock 50 MHz
+ ---motones sim project uses following clock.
+ --cpu clock = base clock / 24 = 2.08 MHz (480 ns / cycle)
+ --ppu clock = base clock / 8
+ --vga clock = base clock / 2
+ --mem clock = base clock
+
base_clk_n <= not base_clk;
- ---base clock 25 MHz = VGA clock.
+
cpu_clk_old <= not cpu_clk_new;
cpu_clk <= cpu_clk_new;
- ppu_clk <= not loop2(0);
- vga_clk <= not loop2(0);
- cpu_we_n <= '0' when loop6 = "001" else
- '0' when loop6 = "100" else
- '1';
- ppu_clk_cnt : counter_register generic map (1) port map
- (base_clk, reset_n, '0', '1', (others=>'0'), loop2);
+ ppu_clk <= loop8(2);
+ vga_clk <= not loop8(0);
+ mem_clk <= base_clk;
+
+ cpu_we_n <= '0' when loop24 = "00011" else
+ '0' when loop24 = "01111" else
+ '1';
+ ppu_clk_cnt : counter_register generic map (3) port map
+ (base_clk, reset_n, '0', '1', (others=>'0'), loop8);
- cpu_clk_cnt : counter_register generic map (3) port map
- (base_clk_n, cpu_cnt_rst_n, '0', '1', (others=>'0'), loop6);
+ cpu_clk_cnt : counter_register generic map (5) port map
+ (base_clk_n, cpu_cnt_rst_n, '0', '1', (others=>'0'), loop24);
- cpu_clk_cnt2 : d_flip_flop_bit port map
+ cpu_clk_inst : d_flip_flop_bit port map
(base_clk, reset_n, '1', cpu_we_n, cpu_clk_old, cpu_clk_new);
clock_p : process (base_clk)
cpu_cnt_rst_n <= '0';
else
if (base_clk'event and base_clk = '1') then
- if (loop6 = "101") then
+ if (loop24 = "10111") then
cpu_cnt_rst_n <= '0';
else
cpu_cnt_rst_n <= '1';
\r
\r
base_clk : in std_logic;\r
--- base_clk_27mhz : in std_logic;\r
+ base_clk_27mhz : in std_logic;\r
rst_n : in std_logic;\r
h_sync_n : out std_logic;\r
v_sync_n : out std_logic;\r
nes_b \r
);\r
\r
--- vga_clk_gen_inst : vga_clk_gen\r
--- PORT map\r
--- (\r
--- base_clk_27mhz, vga_clk_pll\r
--- );\r
+ vga_clk_gen_inst : vga_clk_gen\r
+ PORT map\r
+ (\r
+ base_clk_27mhz, vga_clk_pll\r
+ );\r
\r
\r
vga_ctl_inst : vga_ctl\r
port map ( ppu_clk ,\r
--vga_clk_pll, \r
- ppu_clk ,\r
- --vga_clk ,\r
+ --ppu_clk ,\r
+ vga_clk ,\r
rst_n ,\r
pos_x ,\r
pos_y ,\r
\r
\r
add wave -divider vga_out\r
+\r
+add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/pos_x\r
+add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/pos_y\r
+\r
+add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/vga_x\r
+add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/vga_y\r
+\r
add wave sim:/testbench_qt_proj_test5/sim_board/v_sync_n\r
add wave sim:/testbench_qt_proj_test5/sim_board/h_sync_n\r
add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/r\r
add wave -radix hex sim:/testbench_qt_proj_test5/sim_board/b\r
\r
add wave sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/vga_clk\r
-add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/vga_x\r
-add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/vga_y\r
+\r
+\r
#add wave -position end sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/x_res_n\r
#add wave -position end sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/y_res_n\r
#add wave -position end sim:/testbench_qt_proj_test5/sim_board/vga_ctl_inst/y_en_n\r
port map (cnt_clk , x_res_n, '0', '1', (others => '0'), vga_x);
y_inst : counter_register generic map (10, 1)
port map (cnt_clk , y_res_n, y_en_n, '1', (others => '0'), vga_y);
-
p_vga : process (rst_n, vga_clk)
begin
end if;
--sync signal assert.
- if (vga_x >= conv_std_logic_vector((VGA_W + H_FP) * 341/800, 10) and
- vga_x < conv_std_logic_vector((VGA_W + H_FP + H_SP) * 341/800, 10)) then
+ if (vga_x >= conv_std_logic_vector((VGA_W + H_FP) , 10) and
+ vga_x < conv_std_logic_vector((VGA_W + H_FP + H_SP) , 10)) then
h_sync_n <= '0';
else
h_sync_n <= '1';
end if;
- if (vga_y >= conv_std_logic_vector((VGA_H + V_FP) * 262/525, 10) and
- vga_y < conv_std_logic_vector((VGA_H + V_FP + V_SP) * 262/525, 10)) then
+ if (vga_y >= conv_std_logic_vector((VGA_H + V_FP) , 10) and
+ vga_y < conv_std_logic_vector((VGA_H + V_FP + V_SP) , 10)) then
v_sync_n <= '0';
else
v_sync_n <= '1';
end if;
- if (vga_y <=conv_std_logic_vector((VGA_H) * 341/800, 10)) then
- if (vga_x < conv_std_logic_vector((VGA_W) * 262/525, 10)) then
+ if (vga_y <=conv_std_logic_vector((VGA_H) , 10)) then
+ if (vga_x < conv_std_logic_vector((VGA_W) , 10)) then
-- r<=nes_r;
-- g<=nes_g;
-- b<=nes_b;
g<=(others => '0');
b<=(others => '0');
end if;
-
-
-
-
end if;
end process;
-end rtl;
-
-
-
-
--------------------------------------------------------
--------------------------------------------------------
------------ dummy vga outpu device. ------------------
--------------------------------------------------------
--------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.conv_integer;
-use work.motonesfpga_common.all;
-
-entity vga_device is
- port ( vga_clk : in std_logic;
- rst_n : in std_logic;
- h_sync_n : in std_logic;
- v_sync_n : in std_logic;
- r : in std_logic_vector(3 downto 0);
- g : in std_logic_vector(3 downto 0);
- b : in std_logic_vector(3 downto 0)
- );
-end vga_device;
-
-architecture rtl of vga_device is
-
-constant VGA_W : integer := 640;
-constant VGA_H : integer := 480;
-constant VGA_W_MAX : integer := 800;
-constant VGA_H_MAX : integer := 525;
-constant H_FP : integer := 16;
-constant H_SP : integer := 96;
-constant H_BP : integer := 48;
-constant V_FP : integer := 10;
-constant V_SP : integer := 2;
-constant V_BP : integer := 33;
-
-function conv_color_hex (
- r : in std_logic_vector(3 downto 0);
- g : in std_logic_vector(3 downto 0);
- b : in std_logic_vector(3 downto 0)
- ) return string is
-variable tmp1, tmp2, tmp3 : integer;
-variable hex_chr: string (1 to 16) := "0123456789abcdef";
-begin
- tmp1 := conv_integer(r);
- tmp2 := conv_integer(g);
- tmp3 := conv_integer(b);
- return hex_chr(tmp3 + 1) & hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
-end;
-
-procedure write_vga_pipe(msg : string) is
---use std.textio.all;
---use ieee.std_logic_textio.all;
---variable out_l : line;
---file vga_file: TEXT open write_mode is "vga-port";
-begin
--- write(out_l, msg);
--- writeline(vga_file, out_l);
- --d_print("pipe: " & msg);
-end procedure;
-
-
----ival : 0x0000 - 0xffff
-begin
-
- clk_p : process (rst_n, vga_clk, h_sync_n, v_sync_n)
- variable x, y : integer;
- begin
- if (rst_n = '0') then
- x := 0;
- y := 0;
- --d_print("vga_device: ****");
- else
- if (vga_clk'event and vga_clk = '1') then
- if ( x < VGA_W and y < VGA_H) then
- --d_print(conv_color_hex(r, g, b));
- write_vga_pipe(conv_color_hex(b, g, r));
- --write_vga_pipe("0" & conv_hex8(x));
- --d_print("vga_device: rgb out x:" & conv_hex16(x));
- end if;
- if (x = VGA_W_MAX - 1) then
- x := 0;
- y := y + 1;
- else
- x := x + 1;
- end if;
- if (y = VGA_H_MAX - 1) then
- y := 0;
- end if;
- end if;
+--
+--constant VGA_W : integer := 256;
+--constant VGA_H : integer := 240;
+--constant VGA_W_MAX : integer := 341;
+--constant VGA_H_MAX : integer := 262;
+--
+--constant H_SP : integer := (95 / 2);
+--constant H_FP : integer := (15 / 2);
+--
+--constant V_SP : integer := (2 / 2);
+--constant V_FP : integer := (10 / 2);
+--
+--begin
+--
+-- p_vga : process (rst_n, vga_clk)
+-- begin
+-- if (rst_n = '0') then
+-- h_sync_n <= '0';
+-- v_sync_n <= '0';
+-- r<=(others => '0');
+-- g<=(others => '0');
+-- b<=(others => '0');
+-- elsif (rising_edge(vga_clk)) then
+--
+-- --sync signal assert.
+-- if (pos_x >= conv_std_logic_vector(VGA_W + H_FP , 9) and
+-- pos_x < conv_std_logic_vector(VGA_W + H_FP + H_SP, 9)) then
+-- h_sync_n <= '0';
+-- else
+-- h_sync_n <= '1';
+-- end if;
+--
+-- if (pos_y >= conv_std_logic_vector(VGA_H + V_FP, 9) and
+-- pos_y < conv_std_logic_vector(VGA_H + V_FP + V_SP, 9)) then
+-- v_sync_n <= '0';
+-- else
+-- v_sync_n <= '1';
+-- end if;
+--
+-- if (pos_y <=conv_std_logic_vector(VGA_H, 9)) then
+-- if (pos_x < conv_std_logic_vector(VGA_W, 9)) then
+-- r<=(others => '1');
+-- g<=(others => '1');
+-- b<=(others => '1');
+-- else
+-- r<=(others => '0');
+-- g<=(others => '0');
+-- b<=(others => '0');
+-- end if;
+-- else
+-- r<=(others => '0');
+-- g<=(others => '0');
+-- b<=(others => '0');
+-- end if;
+-- end if;
+-- end process;
+end rtl;
- if (h_sync_n'event and h_sync_n = '0') then
- --d_print("vga_device: h_sync");
- write_vga_pipe("---");
- x := VGA_W + H_FP + 1;
- end if;
- if (v_sync_n'event and v_sync_n = '0') then
- --d_print("vga_device: v_sync");
- write_vga_pipe("___");
- y := VGA_H + V_FP + 1;
- end if;
- end if;
- end process;
-end rtl;
\r
altpll_component : altpll\r
GENERIC MAP (\r
- clk0_divide_by => 15,\r
+ clk0_divide_by => 27,\r
clk0_duty_cycle => 50,\r
- clk0_multiply_by => 14,\r
+ clk0_multiply_by => 25,\r
clk0_phase_shift => "0",\r
compensate_clock => "CLK0",\r
inclk0_input_frequency => 37037,\r
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"\r
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"\r
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"\r
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.200001"\r
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"\r
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"\r
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"\r
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"\r
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"\r
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"\r
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"\r
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.20000000"\r
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"\r
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"\r
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"\r
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"\r
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"\r
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"\r
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all\r
--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15"\r
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"\r
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"\r
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14"\r
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"\r
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"\r
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"\r
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"\r
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