* sid-cpu.scm (cgen-desc.h): Ditto.
* enum.scm (enum-builtin!): New function.
* read.scm (reader-install-builtin!): Call it.
* rtl-c.scm (s-convop): Delete, replaced with ...
(s-int-convop, s-float-convop): ... new fns.
(ext, zext, trunc): Update.
(fext, ftrunc, float, ufloat, fix, ufix): Update.
* rtx-funcs.scm (fext, ftrunc, float, ufloat, fix, ufix): New parameter
`how'.
* cpu/mep-fmax.cpu (fcvtsw): Update.
* cpu/sh.cpu (h-fsd, h-fmov): Update.
* doc/rtl.texi (float-convop): Update.
* frv.cpu (floating-point-conversion): Update call to fp conv op.
(floating-point-dual-conversion, ne-floating-point-dual-conversion,
conditional-floating-point-conversion, ne-floating-point-conversion,
float-parallel-mul-add-double-semantics): Ditto.
2010-01-24 Doug Evans <dje@sebabeach.org>
+ * desc-cpu.scm (cgen-desc.h): Don't print virtual enums.
+ * sid-cpu.scm (cgen-desc.h): Ditto.
+ * enum.scm (enum-builtin!): New function.
+ * read.scm (reader-install-builtin!): Call it.
+ * rtl-c.scm (s-convop): Delete, replaced with ...
+ (s-int-convop, s-float-convop): ... new fns.
+ (ext, zext, trunc): Update.
+ (fext, ftrunc, float, ufloat, fix, ufix): Update.
+ * rtx-funcs.scm (fext, ftrunc, float, ufloat, fix, ufix): New parameter
+ `how'.
+ * cpu/mep-fmax.cpu (fcvtsw): Update.
+ * cpu/sh.cpu (h-fsd, h-fmov): Update.
+ * doc/rtl.texi (float-convop): Update.
+
* gen-all: Be more consistent with intrinsic generation.
* utils-cgen.scm (<location>): Define using new define-class.
(fmax-conv fceilws #xE #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fceilws" fmax-FRn)))
(fmax-conv ffloorws #xF #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ffloorws" fmax-FRn)))
(fmax-conv fcvtws #x4 #x1 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fcvtws" fmax-FRn)))
-(fmax-conv fcvtsw #x0 #x9 fmax-FRd fmax-FRn-int (set fmax-FRd (float SF fmax-FRn-int)))
+(fmax-conv fcvtsw #x0 #x9 fmax-FRd fmax-FRn-int (set fmax-FRd (float SF FPCONV-DEFAULT fmax-FRn-int)))
;------------------------------------------------------------------------------
; Comparisons
(type register DF (16))
(indices keyword "" (.map -build-freg-name (.iota 16)))
(get (index)
- (if DF prbit (reg h-drc index) (fext DF (reg h-fr index))))
+ (if DF prbit (reg h-drc index) (fext DF FPCONV-DEFAULT (reg h-fr index))))
(set (index newval)
(if prbit
(set (reg h-drc index) newval)
- (set (reg h-frc index) (ftrunc SF newval))))
+ (set (reg h-frc index) (ftrunc SF FPCONV-DEFAULT newval))))
)
(define-pmacro (even x) (eq (and x 1) 0))
(get (index)
(if DF (not szbit)
; single precision operation
- (fext DF (reg h-frc index))
+ (fext DF FPCONV-DEFAULT (reg h-frc index))
; double or extended operation
(if DF (extd index)
(reg h-xd (and index (inv 1)))
(set (index newval)
(if (not szbit)
; single precision operation
- (set (reg h-frc index) (ftrunc SF newval))
+ (set (reg h-frc index) (ftrunc SF FPCONV-DEFAULT newval))
; double or extended operation
(if (extd index)
(set (reg h-xd (and index (inv 1))) newval)
; "MODEL_"
; (append (map list (map obj:name (current-model-list))) '((max))))
;"#define MAX_MODELS ((int) MODEL_MAX)\n\n"
- "/* Enums. */\n\n"
- (string-map gen-decl (current-enum-list))
+ (let ((enums (find (lambda (obj) (not (obj-has-attr? obj 'VIRTUAL)))
+ (current-enum-list))))
+ (if (null? enums)
+ ""
+ (string-list
+ "/* Enums. */\n\n"
+ (string-map gen-decl enums))))
"/* Attributes. */\n\n"
(string-map gen-decl (current-attr-list))
"/* Number of architecture variants. */\n"
wider than @samp{mode}, which also must be an integer mode.
@end itemize
-@item (float-convop mode operand)
+@item (float-convop mode how operand)
Perform a mode->mode conversion operation involving a floating point value.
+Conversions involving floating point values need to specify
+how things like truncation will be performed, e.g., the rounding mode.
+@samp{how} is an rtx of mode @samp{INT} that specifies how the conversion
+will be performed. The interpretation of @samp{how} is architecture-dependent,
+except that a value of zero has a specific meaning:
+If a particular floating-point conversion can only be done one way,
+or if the conversion is to be done the ``default'' way, specify zero
+for @samp{how}.
+What ``the default way'' is is application-dependent.
+
@samp{float-convop} is one of:
@itemize @bullet
to an unsigned integer of mode @samp{mode}.
@end itemize
+An enum is defined that specifies several predefined rounding modes.
+
+@smallexample
+(define-enum
+ (name fpconv-kind)
+ (comment "builtin floating point conversion kinds")
+ (attrs VIRTUAL) ;; let app provide def'n instead of each cpu's desc.h
+ (prefix FPCONV-)
+ (values ((DEFAULT 0)
+ (TIES-TO-EVEN 1)
+ (TIES-TO-AWAY 2)
+ (TOWARD-ZERO 3)
+ (TOWARD-POSITIVE 4)
+ (TOWARD-NEGATIVE 5)))
+)
+@end smallexample
+
@item (cmpop mode operand1 operand2)
Perform a comparison.
(parse-enum-vals context prefix vals)))
)
-; Read an enum description
-; This is the main routine for analyzing enums in the .cpu file.
-; CONTEXT is a <context> object for error messages.
-; ARG-LIST is an associative list of field name and field value.
-; /enum-parse is invoked to create the `enum' object.
+;; Read an enum description
+;; This is the main routine for analyzing enums in the .cpu file.
+;; CONTEXT is a <context> object for error messages.
+;; ARG-LIST is an associative list of field name and field value.
+;; /enum-parse is invoked to create the `enum' object.
+;;
+;; FIXME: Change (values ((foo 42) (bar 43))) to (values (foo 42) (bar 43)).
(define (/enum-read context . arg-list)
(let (
*UNSPECIFIED*
)
+(define (enum-builtin!)
+ ;; Provide FPCONV-DEFAULT == 0 as an enum constant to use as the `how'
+ ;; parameter to the floating point conversion functions.
+ ;; ??? Add standard IEEE rounding modes?
+ (define-enum '(name fpconv-kind)
+ '(comment "builtin floating point conversion kinds")
+ '(attrs VIRTUAL) ;; let app provide def'n instead of each cpu's desc.h
+ '(prefix FPCONV-)
+ '(values ((DEFAULT 0)
+ (TIES-TO-EVEN 1)
+ (TIES-TO-AWAY 2)
+ (TOWARD-ZERO 3)
+ (TOWARD-POSITIVE 4)
+ (TOWARD-NEGATIVE 5))))
+
+ *UNSPECIFIED*
+)
+
(define (enum-finish!)
*UNSPECIFIED*
)
(define (reader-install-builtin!)
; The order here is important.
(attr-builtin!)
+ (enum-builtin!)
(mode-builtin!)
(ifield-builtin!)
(hardware-builtin!)
"))"))))
)
-; Mode conversions.
-; MODE is the mode name.
+;; Integer mode conversions.
+;; MODE is the mode name.
-(define (s-convop estate name mode s1)
- ; Get S1 in its normal mode, then convert.
+(define (s-int-convop estate name mode s1)
+ ;; Get S1 in its normal mode, then convert.
(let ((s (rtl-c-get estate DFLT s1))
(mode (mode:lookup mode)))
(if (and (not (estate-rtl-cover-fns? estate))
(string-append "((" (obj:str-name mode) ")"
" (" (obj:str-name (cx:mode s)) ")"
" (" (cx:c s) "))"))
- (if (or (mode-float? mode)
- (mode-float? (cx:mode s)))
- (cx:make mode
- (string-append "CGEN_CPU_FPU (current_cpu)->ops->"
- (string-downcase name)
- (string-downcase (obj:str-name (rtx-sem-mode (cx:mode s))))
- (string-downcase (obj:str-name (rtx-sem-mode mode)))
- " (CGEN_CPU_FPU (current_cpu), "
- (cx:c s) ")"))
- (cx:make mode
- (string-append name
- (obj:str-name (rtx-sem-mode (cx:mode s)))
- (obj:str-name (rtx-sem-mode mode))
- " (" (cx:c s) ")")))))
+ (cx:make mode
+ (string-append name
+ (obj:str-name (rtx-sem-mode (cx:mode s)))
+ (obj:str-name (rtx-sem-mode mode))
+ " (" (cx:c s) ")"))))
+)
+
+;; Floating point mode conversions.
+;; MODE is the mode name.
+
+(define (s-float-convop estate name mode how1 s1)
+ ;; Get S1 in its normal mode, then convert.
+ (let ((s (rtl-c-get estate DFLT s1))
+ (mode (mode:lookup mode))
+ (how (rtl-c-get estate DFLT how1)))
+ (if (and (not (estate-rtl-cover-fns? estate))
+ (mode:host? (cx:mode s)))
+ (cx:make mode
+ (string-append "((" (obj:str-name mode) ")"
+ " (" (obj:str-name (cx:mode s)) ")"
+ " (" (cx:c s) "))"))
+ (cx:make mode
+ (string-append "CGEN_CPU_FPU (current_cpu)->ops->"
+ (string-downcase name)
+ (string-downcase (obj:str-name (rtx-sem-mode (cx:mode s))))
+ (string-downcase (obj:str-name (rtx-sem-mode mode)))
+ " (CGEN_CPU_FPU (current_cpu), "
+ (cx:c how) ", "
+ (cx:c s) ")"))))
)
; Compare SRC1 and SRC2 in mode MODE.
)
(define-fn ext (*estate* options mode s1)
- (s-convop *estate* "EXT" mode s1)
+ (s-int-convop *estate* "EXT" mode s1)
)
(define-fn zext (*estate* options mode s1)
- (s-convop *estate* "ZEXT" mode s1)
+ (s-int-convop *estate* "ZEXT" mode s1)
)
(define-fn trunc (*estate* options mode s1)
- (s-convop *estate* "TRUNC" mode s1)
+ (s-int-convop *estate* "TRUNC" mode s1)
)
-(define-fn fext (*estate* options mode s1)
- (s-convop *estate* "FEXT" mode s1)
+
+(define-fn fext (*estate* options mode how s1)
+ (s-float-convop *estate* "FEXT" mode how s1)
)
-(define-fn ftrunc (*estate* options mode s1)
- (s-convop *estate* "FTRUNC" mode s1)
+(define-fn ftrunc (*estate* options mode how s1)
+ (s-float-convop *estate* "FTRUNC" mode how s1)
)
-(define-fn float (*estate* options mode s1)
- (s-convop *estate* "FLOAT" mode s1)
+(define-fn float (*estate* options mode how s1)
+ (s-float-convop *estate* "FLOAT" mode how s1)
)
-(define-fn ufloat (*estate* options mode s1)
- (s-convop *estate* "UFLOAT" mode s1)
+(define-fn ufloat (*estate* options mode how s1)
+ (s-float-convop *estate* "UFLOAT" mode how s1)
)
-(define-fn fix (*estate* options mode s1)
- (s-convop *estate* "FIX" mode s1)
+(define-fn fix (*estate* options mode how s1)
+ (s-float-convop *estate* "FIX" mode how s1)
)
-(define-fn ufix (*estate* options mode s1)
- (s-convop *estate* "UFIX" mode s1)
+(define-fn ufix (*estate* options mode how s1)
+ (s-float-convop *estate* "UFIX" mode how s1)
)
(define-fn eq (*estate* options mode s1 s2)
; ...
;)
\f
-; Conversions.
+;; Integer conversions.
(drn (ext &options &mode s1)
#f
UNARY
#f
)
-(drn (fext &options &mode s1)
+
+;; Conversions involving floating point values.
+
+(drn (fext &options &mode how s1)
#f
- (OPTIONS ANYFLOATMODE RTX) (NA NA ANY)
+ (OPTIONS ANYFLOATMODE RTX RTX) (NA NA INT ANY)
UNARY
#f
)
-(drn (ftrunc &options &mode s1)
+(drn (ftrunc &options &mode how s1)
#f
- (OPTIONS ANYFLOATMODE RTX) (NA NA ANY)
+ (OPTIONS ANYFLOATMODE RTX RTX) (NA NA INT ANY)
UNARY
#f
)
-(drn (float &options &mode s1)
+(drn (float &options &mode how s1)
#f
- (OPTIONS ANYFLOATMODE RTX) (NA NA ANY)
+ (OPTIONS ANYFLOATMODE RTX RTX) (NA NA INT ANY)
UNARY
#f
)
-(drn (ufloat &options &mode s1)
+(drn (ufloat &options &mode how s1)
#f
- (OPTIONS ANYFLOATMODE RTX) (NA NA ANY)
+ (OPTIONS ANYFLOATMODE RTX RTX) (NA NA INT ANY)
UNARY
#f
)
-(drn (fix &options &mode s1)
+(drn (fix &options &mode how s1)
#f
- (OPTIONS ANYINTMODE RTX) (NA NA ANY)
+ (OPTIONS ANYINTMODE RTX RTX) (NA NA INT ANY)
UNARY
#f
)
-(drn (ufix &options &mode s1)
+(drn (ufix &options &mode how s1)
#f
- (OPTIONS ANYINTMODE RTX) (NA NA ANY)
+ (OPTIONS ANYINTMODE RTX RTX) (NA NA INT ANY)
UNARY
#f
)
namespace @arch@ {
\n"
- "// Enums.\n\n"
- (lambda () (string-map gen-decl (current-enum-list)))
+ (let ((enums (find (lambda (obj) (not (obj-has-attr? obj 'VIRTUAL)))
+ (current-enum-list))))
+ (if (null? enums)
+ ""
+ (string-list
+ "// Enums.\n\n"
+ (string-map gen-decl enums))))
/gen-attr-decls
/gen-insn-attr-decls
+2010-01-24 Doug Evans <dje@sebabeach.org>
+
+ * frv.cpu (floating-point-conversion): Update call to fp conv op.
+ (floating-point-dual-conversion, ne-floating-point-dual-conversion,
+ conditional-floating-point-conversion, ne-floating-point-conversion,
+ float-parallel-mul-add-double-semantics): Ditto.
+
2010-01-05 Doug Evans <dje@sebabeach.org>
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
(.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr))
(.str name "$pack $" src ",$" targ)
(+ pack targ op (rs-null) ope src)
- (set targ (conv mode src))
+ (set targ (conv mode FPCONV-DEFAULT src))
((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert)))
)
)
(.str name "$pack $" src ",$" targ)
(+ pack targ op (rs-null) ope src)
(sequence ()
- (set targ (conv mode src))
+ (set targ (conv mode FPCONV-DEFAULT src))
(set (nextreg targ_hw targ 1)
- (conv mode (nextreg src_hw src 1))))
+ (conv mode FPCONV-DEFAULT (nextreg src_hw src 1))))
((fr500 (unit u-float-dual-convert)))
)
)
(+ pack targ op (rs-null) ope src)
(sequence ()
(c-call VOID "@cpu@_set_ne_index" (index-of targ))
- (set targ (conv mode src))
+ (set targ (conv mode FPCONV-DEFAULT src))
(c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1))
(set (nextreg targ_hw targ 1)
- (conv mode (nextreg src_hw src 1))))
+ (conv mode FPCONV-DEFAULT (nextreg src_hw src 1))))
((fr500 (unit u-float-dual-convert)))
)
)
(.str name "$pack $" src ",$" targ ",$CCi,$cond")
(+ pack targ op (rs-null) CCi cond ope src)
(if (eq CCi (or cond 2))
- (set targ (conv mode src)))
+ (set targ (conv mode FPCONV-DEFAULT src)))
((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert)))
)
)
(+ pack targ op (rs-null) ope src)
(sequence ()
(c-call VOID "@cpu@_set_ne_index" (index-of targ))
- (set targ (conv mode src)))
+ (set targ (conv mode FPCONV-DEFAULT src)))
((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert)))
)
)
(define-pmacro (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ)
(sequence ()
- (set targ (ftrunc SF (mul DF (fext DF arg1) (fext DF arg2))))
+ (set targ (ftrunc SF FPCONV-DEFAULT
+ (mul DF
+ (fext DF FPCONV-DEFAULT arg1)
+ (fext DF FPCONV-DEFAULT arg2))))
(set (nextreg h-fr targ 1)
- (ftrunc SF (add_sub DF
- (fext DF (nextreg h-fr arg1 1))
- (fext DF (nextreg h-fr arg2 1))))))
+ (ftrunc SF FPCONV-DEFAULT
+ (add_sub DF
+ (fext DF FPCONV-DEFAULT (nextreg h-fr arg1 1))
+ (fext DF FPCONV-DEFAULT (nextreg h-fr arg2 1))))))
)
(define-pmacro (float-parallel-mul-add-double
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