unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+ if (!OpInfo) return false;
assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
(OpInfo[1].RegClass == 0 &&
&& "Invalid opcode");
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+ if (!OpInfo) return false;
assert(NumOps >= 3 &&
OpInfo[0].RegClass == ARM::tGPRRegClassID &&
assert(Opcode == ARM::tADDrPCi && "Invalid opcode");
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+ if (!OpInfo) return false;
assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
(OpInfo[1].RegClass == 0 &&
assert(Opcode == ARM::tADDrSPi && "Invalid opcode");
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+ if (!OpInfo) return false;
assert(NumOps >= 3 &&
OpInfo[0].RegClass == ARM::tGPRRegClassID &&
return true;
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+ if (!OpInfo) return false;
+
assert(NumOps == 3 && OpInfo[0].RegClass == 0 &&
OpInfo[1].isPredicate() && OpInfo[2].RegClass == ARM::CCRRegClassID
&& "Exactly 3 operands expected");
unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+ if (!OpInfo) return false;
+
assert(NumOps == 1 && OpInfo[0].RegClass == 0 && "1 imm operand expected");
unsigned Imm11 = getT1Imm11(insn);
unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+ if (!OpInfo) return false;
+
unsigned &OpIdx = NumOpsAdded;
OpIdx = 0;
uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+ if (!OpInfo) return false;
assert(NumOps >= 4
&& OpInfo[0].RegClass == ARM::GPRRegClassID
uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded) {
const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
+ if (!OpInfo) return false;
assert(NumOps >= 2 &&
OpInfo[0].RegClass == ARM::GPRRegClassID &&
unsigned bits15_11 = slice(HalfWord, 15, 11);
// A6.1 Thumb instruction set encoding
- assert((bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) &&
- "Bits [15:11] of first halfword of a Thumb2 instruction out of range");
+ if (!(bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F)) {
+ assert("Bits[15:11] first halfword of Thumb2 instruction is out of range");
+ return false;
+ }
// A6.3 32-bit Thumb instruction encoding