There is an issue with early CSE hitting an assert, so temporarily
remove the pass from the Arm backend.
Bug: https://bugs.llvm.org/show_bug.cgi?id=41081
Differential Revision: https://reviews.llvm.org/D59410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356259
91177308-0d34-0410-b5e6-
96231b3b80d8
TargetPassConfig::addIRPasses();
- // Run the parallel DSP pass and its helpers.
- if (getOptLevel() == CodeGenOpt::Aggressive) {
- addPass(createEarlyCSEPass());
+ // Run the parallel DSP pass.
+ if (getOptLevel() == CodeGenOpt::Aggressive)
addPass(createARMParallelDSPPass());
- }
// Match interleaved memory accesses to ldN/stN intrinsics.
if (TM->getOptLevel() != CodeGenOpt::None)
; CHECK: Scalarize Masked Memory Intrinsics
; CHECK: Expand reduction intrinsics
; CHECK: Dominator Tree Construction
-; CHECK: Early CSE
; CHECK: Natural Loop Information
; CHECK: Scalar Evolution Analysis
; CHECK: Basic Alias Analysis (stateless AA impl)
%inc11.us.i.3.i = add i32 %idx, 4
br label %for.body
+; TODO: CSE, or something similar, is required to remove the duplicate loads.
; CHECK: %for.body
; CHECK: smlad
; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
-; CHECK: smlad
+; CHECK-NOT: smlad r{{.*}}
for.body:
%A3 = phi i32 [ %add9.us.i.3361.i, %for.body ], [ 0, %entry ]
define fastcc i32 @parse_percent_token() nounwind {
entry:
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
-; CHECK: bx lr
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
; Do not convert into single stream code. BranchProbability Analysis assumes
; that branches which goes to "ret" instruction have lower probabilities.
switch i32 undef, label %bb7 [