[VM][PC9801] Re-define DIPSW, to work with V30@PC-9801RA.

diff --git a/source/src/vm/pc9801/cpureg.cpp b/source/src/vm/pc9801/cpureg.cpp
index 49e70c2..333c797 100644 (file)
--- a/source/src/vm/pc9801/cpureg.cpp
+++ b/source/src/vm/pc9801/cpureg.cpp
@@ -23,12 +23,16 @@ namespace PC9801 {
 #if defined(HAS_V30_SUB_CPU)
 void CPUREG::initialize()
 {
+       reg_0f0 = 0;
        use_v30 = false;
-       if((config.dipswitch & (1 << DIPSWITCH_POSITION_CPU_MODE)) != 0) {
+       stat_exthalt = false;
+       if((config.dipswitch & (1 << DIPSWITCH_POSITION_USE_V30)) != 0) {
                enable_v30 = true;
        } else {
                enable_v30 = false;
        }
+//     use_v30 = ((config.dipswitch & (1 << DIPSWITCH_POSITION_CPU_MODE)) != 0);
+//     halt_by_use_v30();
 }
 
 void CPUREG::halt_by_use_v30()
@@ -36,13 +40,9 @@ void CPUREG::halt_by_use_v30()
        if((use_v30)) {
                d_cpu->write_signal(SIG_CPU_HALTREQ, 1, 1);
                d_v30cpu->write_signal(SIG_CPU_HALTREQ, 0, 1);
-               d_cpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
-               d_v30cpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
        } else {
                d_cpu->write_signal(SIG_CPU_HALTREQ, 0, 1);
                d_v30cpu->write_signal(SIG_CPU_HALTREQ, 1, 1);
-               d_cpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
-               d_v30cpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
        }
 }
 #endif
@@ -51,17 +51,8 @@ void CPUREG::halt_by_value(bool val)
 {
        bool haltvalue = (val) ? 0xffffffff : 0x0000000;
 #if defined(HAS_V30_SUB_CPU)
-       if((use_v30)) {
-               d_cpu->write_signal(SIG_CPU_HALTREQ, 0xffffffff, 0xffffffff);
-               d_cpu->write_signal(SIG_CPU_BUSREQ, 0xffffffff, 0xffffffff);
-               d_v30cpu->write_signal(SIG_CPU_HALTREQ, 0, 0xffffffff);
-               d_v30cpu->write_signal(SIG_CPU_BUSREQ, haltvalue, 0xffffffff);
-       } else {
-               d_cpu->write_signal(SIG_CPU_HALTREQ, 0, 0xffffffff);
-               d_cpu->write_signal(SIG_CPU_BUSREQ, haltvalue, 0xffffffff);
-               d_v30cpu->write_signal(SIG_CPU_BUSREQ, 0xffffffff, 0xffffffff);
-               d_v30cpu->write_signal(SIG_CPU_HALTREQ, 0xffffffff, 0xffffffff);
-       }
+       d_cpu->write_signal(SIG_CPU_BUSREQ, haltvalue, 0xffffffff);
+       d_v30cpu->write_signal(SIG_CPU_BUSREQ, haltvalue, 0xffffffff);
 #else
        d_cpu->write_signal(SIG_CPU_BUSREQ, haltvalue, 0xffffffff);
 #endif 
@@ -72,22 +63,28 @@ void CPUREG::reset()
        d_cpu->set_address_mask(0x000fffff);
        init_clock = get_current_clock_uint64() & 0x000000ffffffffff;
        nmi_enabled = false;
-       stat_wait = false;
        stat_exthalt = false;
-       reg_0f0 = 0;
+       reg_0f0 = 0x00;
        if(event_wait >= 0) {
                cancel_event(this, event_wait);
                event_wait = -1;
        }
 
 #if defined(HAS_V30_SUB_CPU)
-//     use_v30 = ((config.cpu_type & 0x02) != 0) ? true : false;
-       use_v30 = false;
+       use_v30 = ((config.dipswitch & (1 << DIPSWITCH_POSITION_CPU_MODE)) != 0);
+//     use_v30 = false;
+       reg_0f0 = (use_v30) ? 0x01 : 0x00;
+//     use_v30 = (((reg_0f0 & 1) != 0) || ((reg_0f0 & 2) != 0) || ((reg_0f0 & 4) != 0));
+       write_signals(&outputs_cputype, (use_v30) ? 0xffffffff : 0x00000000);
+       d_v30cpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
        halt_by_use_v30();
-       write_signals(&outputs_cputype, 0x00);
-#else
-       d_cpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
 #endif
+       d_cpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
+}
+
+uint32_t CPUREG::get_intr_ack()
+{
+       return d_pic->get_intr_ack();
 }
 
 void CPUREG::set_intr_line(bool line, bool pending, uint32_t bit)
@@ -112,15 +109,18 @@ void CPUREG::write_signal(int ch, uint32_t data, uint32_t mask)
                out_debug_log("RESET FROM CPU!!!\n");
                d_cpu->set_address_mask(0x000fffff);
 #if defined(HAS_V30_SUB_CPU)
-               halt_by_use_v30();
+               use_v30 = (((reg_0f0 & 1) != 0) || ((reg_0f0 & 2) != 0) || ((reg_0f0 & 4) != 0));
                write_signals(&outputs_cputype, (use_v30) ? 0xffffffff : 0x00000000);
+//             d_v30cpu->reset();
+               halt_by_use_v30();
 #endif
        } else if(ch == SIG_CPUREG_HALT) {
                stat_exthalt = ((data & mask) != 0);
                halt_by_value(stat_exthalt);
        } else if(ch == SIG_CPUREG_USE_V30) {
 #if defined(HAS_V30_SUB_CPU)
-                       use_v30 = ((data & mask) != 0);
+               use_v30 = ((data & mask) != 0);
+//             write_signals(&outputs_cputype, (use_v30) ? 0xffffffff : 0x00000000);
                //halt_by_use_v30();
                out_debug_log(_T("SIG_CPUREG_USE_V30: V30=%s\n"), (use_v30) ? _T("YES") : _T("NO")); 
 #endif
@@ -139,11 +139,7 @@ void CPUREG::write_io8(uint32_t addr, uint32_t data)
                break;
        case 0x005f:
                // ToDo: Both Pseudo BIOS.
-               d_cpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
-#if defined(HAS_V30_SUB_CPU)
-               d_v30cpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
-#endif
-               stat_wait = true;
+               halt_by_value(true);
                if(event_wait >= 0) {
                        cancel_event(this, event_wait);
                        event_wait = -1;
@@ -155,12 +151,13 @@ void CPUREG::write_io8(uint32_t addr, uint32_t data)
                        // ToDo: Reflesh
                        reg_0f0 = data;
                        d_cpu->set_address_mask(0x000fffff);
+                       d_cpu->reset();
 #if defined(HAS_V30_SUB_CPU)
-//             use_v30 = ((config.cpu_type & 0x02) != 0) ? true : false;
-                       use_v30 = (((data & 1) != 0) || ((data & 2) != 0) || ((data & 4) != 0));
+//                     use_v30 = (((reg_0f0 & 1) != 0) || ((reg_0f0 & 2) != 0) || ((reg_0f0 & 4) != 0));
+//                     write_signals(&outputs_cputype, (use_v30) ? 0xffffffff : 0x00000000);
                        d_v30cpu->reset();
+//                     halt_by_use_v30();
 #endif
-                       d_cpu->reset();
                        out_debug_log(_T("WRITE I/O 00F0h: VAL=%02X\n"), data);
                }
                break;
@@ -306,17 +303,15 @@ void CPUREG::event_callback(int id, int err)
                if(!(stat_exthalt)) {
                        
 #if defined(HAS_V30_SUB_CPU)
-                       halt_by_use_v30();
-#else
-                       d_cpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
+                       d_v30cpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
 #endif
+                       d_cpu->write_signal(SIG_CPU_BUSREQ, 0, 1);
                }
-               stat_wait = false;
                event_wait = -1;
        }
 }
        
-#define STATE_VERSION  3
+#define STATE_VERSION  4
 
 bool CPUREG::process_state(FILEIO* state_fio, bool loading)
 {
@@ -328,7 +323,6 @@ bool CPUREG::process_state(FILEIO* state_fio, bool loading)
        }
        state_fio->StateValue(nmi_enabled);
        state_fio->StateValue(init_clock);
-       state_fio->StateValue(stat_wait);
        state_fio->StateValue(stat_exthalt);
        state_fio->StateValue(reg_0f0); 
        state_fio->StateValue(event_wait);

diff --git a/source/src/vm/pc9801/cpureg.h b/source/src/vm/pc9801/cpureg.h
index 8f771a0..54416cf 100644 (file)
--- a/source/src/vm/pc9801/cpureg.h
+++ b/source/src/vm/pc9801/cpureg.h
@@ -55,6 +55,7 @@ private:
 #endif
        DEVICE* d_mem;
        DEVICE* d_pio;
+       DEVICE* d_pic;
        uint8_t reg_0f0;
        bool nmi_enabled;
        int event_wait;
@@ -95,6 +96,8 @@ public:
        
        // unique function
        void set_intr_line(bool line, bool pending, uint32_t bit);
+       uint32_t get_intr_ack();
+
 #if defined(UPPER_I386)
        void set_context_cpu(I386* device)
 #elif defined(HAS_I86) || defined(HAS_I186) || defined(HAS_I88)
@@ -124,6 +127,10 @@ public:
        {
                d_pio = device;
        }
+       void set_context_pic(DEVICE* device)
+       {
+               d_pic = device;
+       }
        void set_context_cputype(DEVICE* device, int id, uint32_t mask, int shift)
        {
                register_output_signal(&outputs_cputype, device, id, mask, shift);

diff --git a/source/src/vm/pc9801/dipsw.cpp b/source/src/vm/pc9801/dipsw.cpp
index c802fa5..841dad5 100644 (file)
--- a/source/src/vm/pc9801/dipsw.cpp
+++ b/source/src/vm/pc9801/dipsw.cpp
@@ -26,6 +26,7 @@ namespace PC9801 {
 void DIPSWITCH::initialize()
 {
        update_dipswitch();
+       update_ports();
 }
 
 void DIPSWITCH::reset()
@@ -40,14 +41,7 @@ void DIPSWITCH::reset()
 #else
        port_c3 |= 0x08; // MODSW, 1 = Normal Mode, 0 = Hirezo Mode
 #endif
-#if defined(USE_CPU_TYPE)
-       #if defined(HAS_V30_SUB_CPU)
-               if(config.cpu_type & 0x02) {// V30 or V33
-                       port_c3 |= 0x04;
-               }
-       #endif
-#endif
-       pio_mouse->write_signal(SIG_I8255_PORT_C, port_c3, 0x0c);
+       pio_mouse->write_signal(SIG_I8255_PORT_C, port_c3, 0x08);
 
 }
 
@@ -56,16 +50,19 @@ void DIPSWITCH::update_dipswitch()
        sw1 = 0;
        sw2 = 0;
        sw3 = 0;
-#if 1 /* HARDWARE DIP SWITCH */
+       /* HARDWARE DIP SWITCH */
        sw1 |= (((config.dipswitch & (0xff << 8)) >> 8) & 0xff);
-#if 1
        sw1 &= 0xfe;
+#if defined(SUPPORT_HIRESO)
        sw1 |= ((config.monitor_type == 0) ? 0x01 : 0x00);
-#endif
+       sw3 |= ((config.monitor_type == 0) ? 0x08 : 0x00);
+#else
+       sw1 |= 0x01;
+       sw3 |= 0x08;
+#endif 
        sw2 |= (((config.dipswitch & (0xff << 16)) >> 16) & 0xff);
        sw2 = (sw2 & 0x0d) | ((~sw2) & 0xf2); 
-       sw3 |= (((config.dipswitch & (0xff << 24)) >> 24) & 0x7f); 
-#endif
+       sw3 |= (((config.dipswitch & (0xff << 24)) >> 24) & 0xf7);
 }
 
 void DIPSWITCH::update_ports()
@@ -174,14 +171,8 @@ void DIPSWITCH::update_ports()
                port_c |= (((sw1 & (1 << 5)) != 0) ? 0x02 : 0x00); // SW 1-6
                port_c |= (((sw1 & (1 << 4)) != 0) ? 0x01 : 0x00); // SW 1-5
        #endif
-               pio_mouse->write_signal(SIG_I8255_PORT_B, port_c, (0x08 | 0x02 | 0x01));
-       #if defined(HAS_V30_SUB_CPU) && defined(USE_CPU_TYPE)
-               if(config.cpu_type & 0x02) {// V30 or V33
-                       pio_mouse->write_signal(SIG_I8255_PORT_C, 0x04, 0x04);
-               } else {
-                       pio_mouse->write_signal(SIG_I8255_PORT_C, 0x00, 0x04);
-               }
-       #endif
+               port_c |= (((sw3 & (1 << 7)) != 0) ? 0x04 : 0x00); // SW 3-8
+               pio_mouse->write_signal(SIG_I8255_PORT_B, port_c, (0x08 | 0x04 | 0x02 | 0x01));
 #endif
        }               
 }

diff --git a/source/src/vm/pc9801/pc9801.cpp b/source/src/vm/pc9801/pc9801.cpp
index d1ffde4..9c30c99 100644 (file)
--- a/source/src/vm/pc9801/pc9801.cpp
+++ b/source/src/vm/pc9801/pc9801.cpp
@@ -372,7 +372,7 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu)
 #endif
        event->set_context_cpu(cpu, cpu_clocks);
 #if defined(HAS_V30_SUB_CPU)
-       if((config.dipswitch & (1 << DIPSWITCH_POSITION_CPU_MODE)) != 0) { // You should add manually.
+       if((config.dipswitch & (1 << DIPSWITCH_POSITION_USE_V30)) != 0) { // You should add manually.
                event->set_context_cpu(v30cpu, 7987248);
        }
 #endif 
@@ -591,7 +591,9 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu)
        // cpu bus
        cpu->set_context_mem(memory);
        cpu->set_context_io(io);
+#if !defined(HAS_V30_SUB_CPU)
        cpu->set_context_intr(pic);
+#endif
 #ifdef SINGLE_MODE_DMA
        cpu->set_context_dma(dma);
 #endif
@@ -601,11 +603,13 @@ VM::VM(EMU* parent_emu) : VM_TEMPLATE(parent_emu)
 
 #if defined(HAS_V30_SUB_CPU)
        // cpu bus
+       cpu->set_context_intr(cpureg);
        v30cpu->set_context_mem(memory);
        v30cpu->set_context_io(io);
-       v30cpu->set_context_intr(pic);
+       v30cpu->set_context_intr(cpureg);
+       cpureg->set_context_pic(pic);
        #ifdef SINGLE_MODE_DMA
-       //v30cpu->set_context_dma(dma); // DMA may be within MAIN CPU.
+       v30cpu->set_context_dma(dma); // DMA may be within MAIN CPU.
        #endif
        #ifdef USE_DEBUGGER
        v30cpu->set_context_debugger(new DEBUGGER(this, emu));
@@ -1972,9 +1976,7 @@ bool VM::is_frame_skippable()
 
 void VM::update_config()
 {
-       if((config.cpu_type & 2) == 0) { // This don't change if using V30CPU.
-               set_cpu_clock_with_switch(config.cpu_type);
-       }
+       set_cpu_clock_with_switch(config.cpu_type);
 #if defined(USE_MONITOR_TYPE)
        set_wait(config.monitor_type, config.cpu_type);
 #else

diff --git a/source/src/vm/pc9801/pc9801.h b/source/src/vm/pc9801/pc9801.h
index e45ce8f..3ad0540 100644 (file)
--- a/source/src/vm/pc9801/pc9801.h
+++ b/source/src/vm/pc9801/pc9801.h
@@ -140,6 +140,7 @@
        // unknown machines
 #endif
 
+#define DIPSWITCH_POSITION_USE_V30         (0 + 8 - 1)
 // DIPSW POSITION
 // DIPSW1: 8-15
 #define DIPSWITCH_POSITION_HIGH_RESO       (8 + 1 - 1)