Fix Formatting.

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index a435667..31ffd7c 100644 (file)
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2000-12-12  Nick Clifton  <nickc@redhat.com>
+
+       * mips.h: Fix formatting.
+
 Mon Dec 11 10:56:58 2000  Jeffrey A Law  (law@cygnus.com)
 
        * hppa.h (DT_HP_*): Define relative to OLD_DT_LOOS for hpux

diff --git a/include/elf/mips.h b/include/elf/mips.h
index bfa03f1..4446512 100644 (file)
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -122,13 +122,13 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_ARCH_4          0x30000000
 
 /* -mips5 code.  */
-#define E_MIPS_ARCH_5         0x40000000
+#define E_MIPS_ARCH_5           0x40000000
 
 /* -mips32 code.  */
-#define E_MIPS_ARCH_32                0x50000000
+#define E_MIPS_ARCH_32          0x50000000
 
 /* -mips64 code.  */
-#define E_MIPS_ARCH_64                0x60000000
+#define E_MIPS_ARCH_64          0x60000000
 
 /* The ABI of the file.  Also see EF_MIPS_ABI2 above. */
 #define EF_MIPS_ABI            0x0000F000

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index e1a3b29..dc1b204 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2000-12-12  Nick Clifton  <nickc@redhat.com>
+
+       * mips.h: Fix formatting.
+
 2000-12-01  Chris Demetriou  <cgd@sibyte.com>
 
         mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index af6c66c..c493d08 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -133,7 +133,6 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define OP_SH_CODE19           6       /* 19 bit wait code.  */
 #define OP_MASK_CODE19         0x7ffff
 
-
 /* This structure holds information for a particular instruction.  */
 
 struct mips_opcode
@@ -322,11 +321,11 @@ struct mips_opcode
 /* LSI R4010 instruction.  */
 #define INSN_4010                 0x00020000
 /* NEC VR4100 instruction.  */
-#define INSN_4100                   0x00040000
+#define INSN_4100                 0x00040000
 /* Toshiba R3900 instruction.  */
-#define INSN_3900                   0x00080000
+#define INSN_3900                 0x00080000
 /* 32-bit code running on a ISA3+ CPU.  */
-#define INSN_GP32                   0x00100000
+#define INSN_GP32                 0x00100000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */