SSE_CVT_SS2SI_32>,
XS, VEX, VEX_LIG;
defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
- "cvttss2si\t{$src, $dst|$dst, $src}",
+ "cvttss2si{q}\t{$src, $dst|$dst, $src}",
SSE_CVT_SS2SI_64>,
XS, VEX, VEX_W, VEX_LIG;
defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
SSE_CVT_SD2SI>,
XD, VEX, VEX_LIG;
defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
- "cvttsd2si\t{$src, $dst|$dst, $src}",
+ "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
SSE_CVT_SD2SI>,
XD, VEX, VEX_W, VEX_LIG;
XS, VEX_4V, VEX_W, VEX_LIG;
defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
XD, VEX_4V, VEX_LIG;
-defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
- XD, VEX_4V, VEX_LIG;
defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
XD, VEX_4V, VEX_W, VEX_LIG;
+def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
+ (VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
+def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
+ (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
+
let Predicates = [HasAVX], AddedComplexity = 1 in {
def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
(VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
}
defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
- f128mem, load, "cvtsd2si", SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
+ f128mem, load, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
- int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si",
+ int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si{q}",
SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
SSE_CVT_Scalar, 0>, XS, VEX_4V;
defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
- int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss",
+ int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
SSE_CVT_Scalar, 0>, XS, VEX_4V,
VEX_W;
defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
SSE_CVT_Scalar, 0>, XD, VEX_4V;
defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
- int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd",
+ int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
SSE_CVT_Scalar, 0>, XD,
VEX_4V, VEX_W;
"cvtsi2sd", SSE_CVT_Scalar>, XD;
defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
int_x86_sse2_cvtsi642sd, i64mem, loadi64,
- "cvtsi2sd", SSE_CVT_Scalar>, XD, REX_W;
+ "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
}
/// SSE 1 Only
SSE_CVT_SS2SI_32>, XS, VEX;
defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
int_x86_sse_cvttss2si64, f32mem, load,
- "cvttss2si", SSE_CVT_SS2SI_64>,
+ "cvttss2si{q}", SSE_CVT_SS2SI_64>,
XS, VEX, VEX_W;
defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
XD, VEX;
defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
int_x86_sse2_cvttsd2si64, f128mem, load,
- "cvttsd2si", SSE_CVT_SD2SI>,
+ "cvttsd2si{q}", SSE_CVT_SD2SI>,
XD, VEX, VEX_W;
defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
f32mem, load, "cvttss2si",
"cvtss2si{l}\t{$src, $dst|$dst, $src}",
SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
- "cvtss2si\t{$src, $dst|$dst, $src}",
+ "cvtss2si{q}\t{$src, $dst|$dst, $src}",
SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
"vcvtdq2ps\t{$src, $dst|$dst, $src}",
// CHECK: encoding: [0xc5,0xf8,0x77]
vzeroupper
-// CHECK: vcvtsd2si %xmm4, %ecx
+// CHECK: vcvtsd2sil %xmm4, %ecx
// CHECK: encoding: [0xc5,0xfb,0x2d,0xcc]
- vcvtsd2si %xmm4, %ecx
+ vcvtsd2sil %xmm4, %ecx
-// CHECK: vcvtsd2si (%ecx), %ecx
+// CHECK: vcvtsd2sil (%ecx), %ecx
// CHECK: encoding: [0xc5,0xfb,0x2d,0x09]
- vcvtsd2si (%ecx), %ecx
+ vcvtsd2sil (%ecx), %ecx
-// CHECK: vcvtsi2sdl (%ebp), %xmm0, %xmm7
+// CHECK: vcvtsi2sd (%ebp), %xmm0, %xmm7
// CHECK: encoding: [0xc5,0xfb,0x2a,0x7d,0x00]
- vcvtsi2sdl (%ebp), %xmm0, %xmm7
+ vcvtsi2sd (%ebp), %xmm0, %xmm7
-// CHECK: vcvtsi2sdl (%esp), %xmm0, %xmm7
+// CHECK: vcvtsi2sd (%esp), %xmm0, %xmm7
// CHECK: encoding: [0xc5,0xfb,0x2a,0x3c,0x24]
- vcvtsi2sdl (%esp), %xmm0, %xmm7
+ vcvtsi2sd (%esp), %xmm0, %xmm7
// CHECK: vlddqu (%eax), %ymm2
// CHECK: encoding: [0xc5,0xff,0xf0,0x10]
// CHECK: encoding: [0xc4,0x63,0x2d,0x06,0x18,0x07]
vperm2f128 $7, (%rax), %ymm10, %ymm11
-// CHECK: vcvtsd2si %xmm8, %r8d
+// CHECK: vcvtsd2sil %xmm8, %r8d
// CHECK: encoding: [0xc4,0x41,0x7b,0x2d,0xc0]
- vcvtsd2si %xmm8, %r8d
+ vcvtsd2sil %xmm8, %r8d
-// CHECK: vcvtsd2si (%rcx), %ecx
+// CHECK: vcvtsd2sil (%rcx), %ecx
// CHECK: encoding: [0xc5,0xfb,0x2d,0x09]
- vcvtsd2si (%rcx), %ecx
+ vcvtsd2sil (%rcx), %ecx
-// CHECK: vcvtss2si %xmm4, %rcx
+// CHECK: vcvtss2siq %xmm4, %rcx
// CHECK: encoding: [0xc4,0xe1,0xfa,0x2d,0xcc]
- vcvtss2si %xmm4, %rcx
+ vcvtss2siq %xmm4, %rcx
-// CHECK: vcvtss2si (%rcx), %r8
+// CHECK: vcvtss2siq (%rcx), %r8
// CHECK: encoding: [0xc4,0x61,0xfa,0x2d,0x01]
- vcvtss2si (%rcx), %r8
+ vcvtss2siq (%rcx), %r8
-// CHECK: vcvtsi2sdl %r8d, %xmm8, %xmm15
+// CHECK: vcvtsi2sd %r8d, %xmm8, %xmm15
// CHECK: encoding: [0xc4,0x41,0x3b,0x2a,0xf8]
- vcvtsi2sdl %r8d, %xmm8, %xmm15
+ vcvtsi2sd %r8d, %xmm8, %xmm15
-// CHECK: vcvtsi2sdl (%rbp), %xmm8, %xmm15
+// CHECK: vcvtsi2sd (%rbp), %xmm8, %xmm15
// CHECK: encoding: [0xc5,0x3b,0x2a,0x7d,0x00]
- vcvtsi2sdl (%rbp), %xmm8, %xmm15
+ vcvtsi2sd (%rbp), %xmm8, %xmm15
// CHECK: vcvtsi2sdq %rcx, %xmm4, %xmm6
// CHECK: encoding: [0xc4,0xe1,0xdb,0x2a,0xf1]
// CHECK: encoding: [0xc4,0xe1,0xda,0x2a,0x31]
vcvtsi2ssq (%rcx), %xmm4, %xmm6
-// CHECK: vcvttsd2si %xmm4, %rcx
+// CHECK: vcvttsd2siq %xmm4, %rcx
// CHECK: encoding: [0xc4,0xe1,0xfb,0x2c,0xcc]
- vcvttsd2si %xmm4, %rcx
+ vcvttsd2siq %xmm4, %rcx
-// CHECK: vcvttsd2si (%rcx), %rcx
+// CHECK: vcvttsd2siq (%rcx), %rcx
// CHECK: encoding: [0xc4,0xe1,0xfb,0x2c,0x09]
- vcvttsd2si (%rcx), %rcx
+ vcvttsd2siq (%rcx), %rcx
-// CHECK: vcvttss2si %xmm4, %rcx
+// CHECK: vcvttss2siq %xmm4, %rcx
// CHECK: encoding: [0xc4,0xe1,0xfa,0x2c,0xcc]
- vcvttss2si %xmm4, %rcx
+ vcvttss2siq %xmm4, %rcx
-// CHECK: vcvttss2si (%rcx), %rcx
+// CHECK: vcvttss2siq (%rcx), %rcx
// CHECK: encoding: [0xc4,0xe1,0xfa,0x2c,0x09]
- vcvttss2si (%rcx), %rcx
+ vcvttss2siq (%rcx), %rcx
// CHECK: vlddqu (%rax), %ymm12
// CHECK: encoding: [0xc5,0x7f,0xf0,0x20]