[ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205890 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
index f702522..749cb52 100644 (file)
--- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
+++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
@@ -96,7 +96,9 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
         AsmMnemonic = IsSigned ? "sxth" : "uxth";
         break;
       case 31:
-        AsmMnemonic = IsSigned ? "sxtw" : "uxtw";
+        // *xtw is only valid for 64-bit operations.
+        if (Opcode == ARM64::SBFMXri || Opcode == ARM64::UBFMXri)
+          AsmMnemonic = IsSigned ? "sxtw" : "uxtw";
         break;
       }
 

diff --git a/test/MC/Disassembler/ARM64/canonical-form.txt b/test/MC/Disassembler/ARM64/canonical-form.txt
index 80c032d..09467a3 100644 (file)
--- a/test/MC/Disassembler/ARM64/canonical-form.txt
+++ b/test/MC/Disassembler/ARM64/canonical-form.txt
@@ -15,3 +15,7 @@
 0x1f 0x00 0x00 0x11
 
 # CHECK: mov wsp, w0
+
+0x00 0x7c 0x00 0x13
+
+# CHECK: asr   w0, w0, #0