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x86/amd-iommu: Export cache-coherency capability
author
Joerg Roedel
<joerg.roedel@amd.com>
Tue, 27 Jul 2010 15:14:24 +0000
(17:14 +0200)
committer
Joerg Roedel
<joerg.roedel@amd.com>
Tue, 27 Jul 2010 15:14:24 +0000
(17:14 +0200)
This patch exports the capability of the AMD IOMMU to force
cache coherency of DMA transactions through the IOMMU-API.
This is required to disable some nasty hacks in KVM when
this capability is not available.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
arch/x86/kernel/amd_iommu.c
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diff --git
a/arch/x86/kernel/amd_iommu.c
b/arch/x86/kernel/amd_iommu.c
index
29dd3b9
..
fa044e1
100644
(file)
--- a/
arch/x86/kernel/amd_iommu.c
+++ b/
arch/x86/kernel/amd_iommu.c
@@
-2572,6
+2572,11
@@
static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
unsigned long cap)
{
+ switch (cap) {
+ case IOMMU_CAP_CACHE_COHERENCY:
+ return 1;
+ }
+
return 0;
}