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rts added
authorastoria-d <astoria-d@mail.goo.ne.jp>
Sat, 17 Sep 2016 07:15:38 +0000 (16:15 +0900)
committerastoria-d <astoria-d@mail.goo.ne.jp>
Sat, 17 Sep 2016 07:15:38 +0000 (16:15 +0900)
de0_cv_nes/mos6502.vhd
de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do

index c0ca0e6..161f6dc 100644 (file)
@@ -122,7 +122,7 @@ constant inst_decode_rom : cpu_state_array := (
   --28          29          2a          2b          2c          2d          2e          2f\r
     ST_A52_T1,  ST_A21_T1,  ST_A1_T1,   ST_INV,     ST_A23_T1,  ST_A23_T1,  ST_A42_T1,  ST_INV,\r
   --30          31          32          33          34          35          36          37\r
-    ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_INV,     ST_A43_T1,  ST_INV,\r
+    ST_A58_T1,  ST_A27_T1,  ST_INV,     ST_INV,     ST_A26_T1,  ST_A26_T1,  ST_A43_T1,  ST_INV,\r
   --38          39          3a          3b          3c          3d          3e          3f\r
     ST_A1_T1,   ST_A25_T1,  ST_INV,     ST_INV,     ST_INV,     ST_A25_T1,  ST_A44_T1,  ST_INV,\r
   --40          41          42          43          44          45          46          47\r
@@ -1048,6 +1048,7 @@ end;
                 reg_main_state = ST_A561_T1 or\r
                 reg_main_state = ST_A562_T1 or\r
                 reg_main_state = ST_A562_T2 or\r
+                reg_main_state = ST_A57_T1 or\r
                 reg_main_state = ST_A58_T1) then\r
                 if (reg_sub_state = ST_SUB00) then\r
                     --fetch next.\r
@@ -1058,6 +1059,7 @@ end;
                     --pc move next.\r
                     pc_inc;\r
                 end if;\r
+\r
            --jsr.\r
             elsif (reg_main_state = ST_A53_T2) then\r
                 --sp out (discarded.)\r
@@ -1101,6 +1103,36 @@ end;
                     reg_pc_l    <= reg_idl_l;\r
                     reg_pc_h    <= reg_idl_h;\r
                 end if;\r
+\r
+           --rts.\r
+            elsif (reg_main_state = ST_A57_T2) then\r
+                --sp out (discarded.)\r
+                reg_addr    <= "00000001" & reg_sp;\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
+            elsif (reg_main_state = ST_A57_T3) then\r
+                --pull pcl\r
+                if (reg_sub_state = ST_SUB00) then\r
+                    reg_addr    <= "00000001" & reg_sp + 1;\r
+                    reg_d_out   <= (others => 'Z');\r
+                    reg_r_nw    <= '1';\r
+                elsif (reg_sub_state = ST_SUB70) then\r
+                    reg_pc_l    <= reg_d_in;\r
+                end if;\r
+            elsif (reg_main_state = ST_A57_T4) then\r
+                --pull pch\r
+                if (reg_sub_state = ST_SUB00) then\r
+                    reg_addr    <= "00000001" & reg_sp + 2;\r
+                    reg_d_out   <= (others => 'Z');\r
+                    reg_r_nw    <= '1';\r
+                elsif (reg_sub_state = ST_SUB70) then\r
+                    reg_pc_h    <= reg_d_in;\r
+                end if;\r
+            elsif (reg_main_state = ST_A57_T5) then\r
+                --pc out (discarded.)\r
+                reg_addr    <= reg_pc_h & reg_pc_l;\r
+                reg_d_out   <= (others => 'Z');\r
+                reg_r_nw    <= '1';\r
             end if;--if (reg_main_state = ST_RS_T0) then\r
         end if;--if (pi_rst_n = '0') then\r
     end process;\r
@@ -1171,9 +1203,8 @@ end;
                     reg_sp <= reg_idl_l;\r
                 end if;\r
             elsif (reg_main_state = ST_A53_T3 or\r
-                reg_main_state = ST_A53_T4-- or\r
-                ) then\r
-                --push\r
+                reg_main_state = ST_A53_T4) then\r
+                --jsr. push pch/pcl.\r
                 if (reg_sub_state = ST_SUB70) then\r
                     reg_sp <= reg_sp - 1;\r
                 end if;\r
index f22dd7a..e694092 100644 (file)
@@ -56,7 +56,7 @@ view signals
 run 12 us\r
 wave zoom full\r
 \r
-run 20 us\r
+run 180 us\r
 \r
 \r
 #################################### PPU part.... ###########################################\r