}
static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ struct ras_err_data *err_data,
struct amdgpu_iv_entry *entry);
static int gfx_v9_0_ecc_late_init(void *handle)
}
static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ struct ras_err_data *err_data,
struct amdgpu_iv_entry *entry)
{
/* TODO ue will trigger an interrupt. */
}
static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
+ struct ras_err_data *err_data,
struct amdgpu_iv_entry *entry)
{
- struct ras_err_data err_data = {0, 0};
kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
if (adev->umc.funcs->query_ras_error_count)
- adev->umc.funcs->query_ras_error_count(adev, &err_data);
+ adev->umc.funcs->query_ras_error_count(adev, err_data);
amdgpu_ras_reset_gpu(adev, 0);
return AMDGPU_RAS_UE;
}
}
static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ struct ras_err_data *err_data,
struct amdgpu_iv_entry *entry);
static int sdma_v4_0_late_init(void *handle)
}
static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
+ struct ras_err_data *err_data,
struct amdgpu_iv_entry *entry)
{
uint32_t instance, err_source;