ret i32 %tmp1
}
+; CHECK: bic r0, r0, r1
+
define i32 @f2(i32 %a, i32 %b) {
%tmp = xor i32 %b, 4294967295
%tmp1 = and i32 %tmp, %a
ret i32 %tmp1
}
+
+; CHECK: bic r0, r0, r1
-; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | grep -E {vmov\\W*r\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | not grep fmrrd
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 | FileCheck %s
@i = weak global i32 0 ; <i32*> [#uses=2]
@u = weak global i32 0 ; <i32*> [#uses=2]
store i16 %tmp, i16* null
ret void
}
+
+; CHECK: vmov d0, r0, r1
+; CHECK-NOT: fmrrd
+
-; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {vsub.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vsub.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {vsub.f32\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NFP1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NFP0
define float @test(float %a, float %b) {
entry:
ret float %0
}
+; VFP2: vsub.f32 s0, s1, s0
+; NFP1: vsub.f32 d0, d1, d0
+; NFP0: vsub.f32 s0, s1, s0
-; RUN: llc < %s -march=arm -mattr=+v6t2 | grep {mls\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\],\\W*r\[0-9\]} | count 1
+; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b, i32 %c) {
%tmp1 = mul i32 %a, %b
%tmp2 = sub i32 %tmp1, %c
ret i32 %tmp2
}
+
+; CHECK: mls r0, r0, r1, r2
-; RUN: llc < %s -march=pic16 | grep {movf \\+@i + 0, \\+W}
+; RUN: llc < %s -march=pic16 | FileCheck %s
target datalayout = "e-p:16:8:8-i8:8:8-i16:8:8-i32:8:8-f32:32:32"
target triple = "pic16-"
store i8 %conv8, i8* %tmp9
ret void
}
+
+; CHECK: movf @i + 0, W
-; RUN: llc < %s -march=ppc32 | \
-; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4
-; RUN: llc < %s -march=ppc32 | not grep rlwinm
-; RUN: llc < %s -march=ppc32 | not grep rlwimi
-; RUN: llc < %s -march=ppc64 | \
-; RUN: grep {stwbrx\\|lwbrx\\|sthbrx\\|lhbrx} | count 4
-; RUN: llc < %s -march=ppc64 | not grep rlwinm
-; RUN: llc < %s -march=ppc64 | not grep rlwimi
+; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32
+; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64
+
define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
%tmp1 = getelementptr i8* %ptr, i32 %off ; <i8*> [#uses=1]
declare i16 @llvm.bswap.i16(i16)
+
+; X32: stwbrx 3, 4, 5
+; X32: lwbrx 3, 3, 4
+; X32: sthbrx 3, 4, 5
+; X32: lhbrx 3, 3, 4
+; X32-NOT: rlwinm
+; X32-NOT: rlwimi
+
+; X32: stwbrx 3, 4, 5
+; X32: lwbrx 3, 3, 4
+; X32: sthbrx 3, 4, 5
+; X32: lhbrx 3, 3, 4
+; X64-NOT: rlwinm
+; X64-NOT: rlwimi
+
-; RUN: llc < %s -march=x86 | grep -A 2 {call.*f} | grep movl
+; RUN: llc < %s -march=x86 | FileCheck %s
; Check the register copy comes after the call to f and before the call to g
; PR3784
%y = phi i32 [ %a, %entry ], [ %aa, %cont ] ; <i32> [#uses=1]
ret i32 %y
}
+
+; CHECK: call{{.*}}f
+; CHECK-NEXT: Llabel1:
+; CHECK-NEXT: movl %eax, %esi
-; RUN: llc < %s -march=x86 -asm-verbose | grep -A 1 lpad | grep Llabel
+; RUN: llc < %s -march=x86 -asm-verbose | FileCheck %s
; Check that register copies in the landing pad come after the EH_LABEL
declare i32 @f()
%v = phi i32 [ %x, %entry ], [ %a, %cont ] ; <i32> [#uses=1]
ret i32 %v
}
+
+; CHECK: lpad
+; CHECK-NEXT: Llabel
-; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=i486 | \
-; RUN: grep {fadd\\|fsub\\|fdiv\\|fmul} | not grep -i ST
-
+; RUN: llc < %s -march=x86 -x86-asm-syntax=intel -mcpu=i486 | FileCheck %s
; Test that the load of the constant is folded into the operation.
%tmp.1 = fadd double %P, 1.230000e+02 ; <double> [#uses=1]
ret double %tmp.1
}
+; CHECK: fadd {{[^sS][^tT]}}
+; CHECK: fadd {{[^sS][^tT]}}
define double @foo_mul(double %P) {
%tmp.1 = fmul double %P, 1.230000e+02 ; <double> [#uses=1]
ret double %tmp.1
}
+; CHECK: fmul {{[^sS][^tT]}}
define double @foo_sub(double %P) {
%tmp.1 = fsub double %P, 1.230000e+02 ; <double> [#uses=1]
%tmp.1 = fdiv double 1.230000e+02, %P ; <double> [#uses=1]
ret double %tmp.1
}
+
+
+; CHECK: fsub {{[^sS][^tT]}}
+; CHECK: fdiv {{[^sS][^tT]}}
+; CHECK: fdiv {{[^sS][^tT]}}
+
-; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | grep -A 1 call | grep -A 1 tailcaller | grep subl | grep 12
+; RUN: llc < %s -mtriple=i686-unknown-linux -tailcallopt | FileCheck %s
; Linux has 8 byte alignment so the params cause stack size 20 when tailcallopt
; is enabled, ensure that a normal fastcc call has matching stack size
ret i32 0
}
-
-
-
+; CHECK: call tailcaller
+; CHECK-NEXT: subl $12
; An integer truncation to i1 should be done with an and instruction to make
; sure only the LSBit survives. Test that this is the case both for a returned
; value and as the operand of a branch.
-; RUN: llc < %s -march=x86 | grep {\\(and\\)\\|\\(test.*\\\$1\\)} | \
-; RUN: count 5
+; RUN: llc < %s -march=x86 | FileCheck %s
define i1 @test1(i32 %X) zeroext {
%Y = trunc i32 %X to i1
ret i1 %Y
}
+; CHECK: andl $1, %eax
define i1 @test2(i32 %val, i32 %mask) {
entry:
ret_false:
ret i1 false
}
+; CHECK: testb $1, %al
define i32 @test3(i8* %ptr) {
%val = load i8* %ptr
cond_false:
ret i32 42
}
+; CHECK: testb $1, %al
define i32 @test4(i8* %ptr) {
%tmp = ptrtoint i8* %ptr to i1
cond_false:
ret i32 42
}
+; CHECK: testb $1, %al
define i32 @test6(double %d) {
%tmp = fptosi double %d to i1
cond_false:
ret i32 42
}
-
+; CHECK: testb $1, %al