drm/i915/dp: Do not enable PSR2 if DSC is enabled

If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.

v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning for DSC and PSR2 enabled together (DK)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181128202628.20238-3-manasi.d.navare@intel.com

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 572e626..2084784 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -75,6 +75,10 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
        if (i915_modparams.enable_psr == -1)
                return false;
 
+       /* Cannot enable DSC and PSR2 simultaneously */
+       WARN_ON(crtc_state->dsc_params.compression_enable &&
+               crtc_state->has_psr2);
+
        switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
        case I915_PSR_DEBUG_FORCE_PSR1:
                return false;
@@ -502,6 +506,16 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
        if (!dev_priv->psr.sink_psr2_support)
                return false;
 
+       /*
+        * DSC and PSR2 cannot be enabled simultaneously. If a requested
+        * resolution requires DSC to be enabled, priority is given to DSC
+        * over PSR2.
+        */
+       if (crtc_state->dsc_params.compression_enable) {
+               DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n");
+               return false;
+       }
+
        if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
                psr_max_h = 4096;
                psr_max_v = 2304;