PCI: qcom: Replace define with standard value

Lots of define are actually already defined in pci_regs.h, directly use
the standard defines.

Link: https://lore.kernel.org/r/20200615210608.21469-13-ansuelsmth@gmail.com
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 17498e6..73d4eed 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -40,11 +40,6 @@
 #define L23_CLK_RMV_DIS                                BIT(2)
 #define L1_CLK_RMV_DIS                         BIT(1)
 
-#define PCIE20_COMMAND_STATUS                  0x04
-#define CMD_BME_VAL                            0x4
-#define PCIE20_DEVICE_CONTROL2_STATUS2         0x98
-#define PCIE_CAP_CPL_TIMEOUT_DISABLE           0x10
-
 #define PCIE20_PARF_PHY_CTRL                   0x40
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK      GENMASK(20, 16)
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)                ((x) << 16)
@@ -73,8 +68,8 @@
 #define CFG_BRIDGE_SB_INIT                     BIT(0)
 
 #define PCIE20_CAP                             0x70
-#define PCIE20_CAP_LINK_CAPABILITIES           (PCIE20_CAP + 0xC)
-#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT        (BIT(10) | BIT(11))
+#define PCIE20_DEVICE_CONTROL2_STATUS2         (PCIE20_CAP + PCI_EXP_DEVCTL2)
+#define PCIE20_CAP_LINK_CAPABILITIES           (PCIE20_CAP + PCI_EXP_LNKCAP)
 #define PCIE20_CAP_LINK_1                      (PCIE20_CAP + 0x14)
 #define PCIE_CAP_LINK1_VAL                     0x2FD7F
 
@@ -1095,15 +1090,15 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
                pcie->parf + PCIE20_PARF_SYS_CTRL);
        writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
 
-       writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
+       writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
        writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
        writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
 
        val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
-       val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;
+       val &= ~PCI_EXP_LNKCAP_ASPMS;
        writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
 
-       writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
+       writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base +
                PCIE20_DEVICE_CONTROL2_STATUS2);
 
        return 0;