arm64: dts: exynos: drop clock-frequency from CPU nodes in TM2

The CPU frequencies are determined by OPP table, so drop the
'clock-frequency' property.  It is not parsed by any driver.

Link: https://lore.kernel.org/r/20221204113839.151816-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0976d2b..47b5ac0 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -89,7 +89,6 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x100>;
-                       clock-frequency = <1300000000>;
                        clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
                        clock-names = "apolloclk";
                        operating-points-v2 = <&cluster_a53_opp_table>;
@@ -108,7 +107,6 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x101>;
-                       clock-frequency = <1300000000>;
                        operating-points-v2 = <&cluster_a53_opp_table>;
                        #cooling-cells = <2>;
                        i-cache-size = <0x8000>;
@@ -125,7 +123,6 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x102>;
-                       clock-frequency = <1300000000>;
                        operating-points-v2 = <&cluster_a53_opp_table>;
                        #cooling-cells = <2>;
                        i-cache-size = <0x8000>;
@@ -142,7 +139,6 @@
                        compatible = "arm,cortex-a53";
                        enable-method = "psci";
                        reg = <0x103>;
-                       clock-frequency = <1300000000>;
                        operating-points-v2 = <&cluster_a53_opp_table>;
                        #cooling-cells = <2>;
                        i-cache-size = <0x8000>;
@@ -159,7 +155,6 @@
                        compatible = "arm,cortex-a57";
                        enable-method = "psci";
                        reg = <0x0>;
-                       clock-frequency = <1900000000>;
                        clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
                        clock-names = "atlasclk";
                        operating-points-v2 = <&cluster_a57_opp_table>;
@@ -178,7 +173,6 @@
                        compatible = "arm,cortex-a57";
                        enable-method = "psci";
                        reg = <0x1>;
-                       clock-frequency = <1900000000>;
                        operating-points-v2 = <&cluster_a57_opp_table>;
                        #cooling-cells = <2>;
                        i-cache-size = <0xc000>;
@@ -195,7 +189,6 @@
                        compatible = "arm,cortex-a57";
                        enable-method = "psci";
                        reg = <0x2>;
-                       clock-frequency = <1900000000>;
                        operating-points-v2 = <&cluster_a57_opp_table>;
                        #cooling-cells = <2>;
                        i-cache-size = <0xc000>;
@@ -212,7 +205,6 @@
                        compatible = "arm,cortex-a57";
                        enable-method = "psci";
                        reg = <0x3>;
-                       clock-frequency = <1900000000>;
                        operating-points-v2 = <&cluster_a57_opp_table>;
                        #cooling-cells = <2>;
                        i-cache-size = <0xc000>;