hblank = true;
halt_flag = false;
cancel_request = false;
+ cancel_bak = false;
firq_backup = false;
irq_backup = false;
displine = 0;
register_event(this, EVENT_FM7SUB_VSTART, 10.0, false, &vstart_event_id);
register_event(this, EVENT_FM7SUB_DISPLAY_NMI, 20000.0, true, &nmi_event_id); // NEXT CYCLE_
sub_busy = true;
+ sub_busy_bak = !sub_busy;
+ do_attention = false;
+ mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0xff, 0xff);
// subcpu->reset();
}
//SUB:D402:R
uint8 DISPLAY::acknowledge_irq(void)
{
- this->do_irq(false);
cancel_request = false;
+ //do_irq(false);
return 0xff;
}
// SUB:D404 : R
uint8 DISPLAY::attention_irq(void)
{
- mainio->write_signal(FM7_MAINIO_SUB_ATTENTION, 0x01, 0x01);
+ do_attention = true;
//printf("DISPLAY: ATTENTION TO MAIN\n");
+ //mainio->write_signal(FM7_MAINIO_SUB_ATTENTION, 0x01, 0x01);
return 0xff;
}
uint8 DISPLAY::reset_subbusy(void)
{
sub_busy = false;
+// mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0, 0xff);
return 0xff;
}
void DISPLAY::set_subbusy(void)
{
sub_busy = true;
+// mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0xff, 0xff);
}
void DISPLAY::event_vline(int v, int clock)
{
+ if(sub_busy_bak != sub_busy) {
+ mainio->write_signal(FM7_MAINIO_SUB_BUSY, sub_busy ? 0xff : 0x00, 0xff);
+ }
+ sub_busy_bak = sub_busy;
+ if(cancel_request != cancel_bak) {
+ do_irq(cancel_request);
+ }
+ cancel_bak = cancel_request;
+ if(do_attention) mainio->write_signal(FM7_MAINIO_SUB_ATTENTION, 0x01, 0x01);
+ do_attention = false;
}
uint32 DISPLAY::read_signal(int id)
case SIG_FM7_SUB_HALT:
if(flag) {
sub_busy = true;
+ //mainio->write_signal(FM7_MAINIO_SUB_BUSY, 0xff, 0xff);
}
- if(cancel_request && flag) {
- restart_subsystem();
- halt_flag = false;
- printf("SUB: HALT : CANCEL\n");
- return;
- }
+ //if(cancel_request && flag) {
+ // restart_subsystem();
+ // halt_flag = false;
+ // printf("SUB: HALT : CANCEL\n");
+ // return;
+ //}
halt_flag = flag;
//printf("SUB: HALT : DID STAT=%d\n", flag);
break;
//printf("MAIN: CANCEL REQUEST TO SUB\n");
if(flag) {
cancel_request = true;
- do_irq(true);
+ //do_irq(true);
}
break;
case SIG_DISPLAY_CLOCK:
tmp_offset_point.d = 0;
offset_point = 0;
halt_flag = false;
+ sub_busy_bak = false;
+ do_attention = false;
}
void DISPLAY::release()
event->set_context_sound(opn[1]);
event->set_context_sound(opn[2]);
event->set_context_sound(drec);
+ event->register_vline_event(display);
+ event->register_vline_event(mainio);
mainio->set_context_maincpu(maincpu);
mainio->set_context_subcpu(subcpu);
private:
bool sub_busy;
+ bool sub_busy_bak;
+ bool do_attention;
uint32 disp_mode;
bool vblank;
bool vsync;
bool subcpu_resetreq;
bool power_on_reset;
bool cancel_request;
+ bool cancel_bak;
DEVICE *ins_led;
DEVICE *kana_led;
#include "../datarec.h"
// TEST
-//#include <SDL2/SDL.h>
+#include <SDL2/SDL.h>
void FM7_MAINIO::initialize()
{
break;
}
this->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
+ sub_busy = false;
}
void FM7_MAINIO::reset()
#if defined(_FM77AV_VARIANTS)
mode320 = false;
sub_monitor_type = 0x00;
+ sub_monitor_bak = sub_monitor_type;
+ display->write_signal(SIG_FM7_SUB_BANK, sub_monitor_type, 0x07);
#endif
#ifdef HAS_MMR
// FD04
//firq_break_key = false; // bit1, ON = '0'.
firq_sub_attention = false; // bit0, ON = '0'.
+ firq_sub_attention_bak = false; // bit0, ON = '0'.
// FD05
extdet_neg = false;
sub_cancel = false; // bit6 : '1' Cancel req.
-
+ sub_halt = false; // bit6 : '1' Cancel req.
+ sub_cancel_bak = !sub_cancel; // bit6 : '1' Cancel req.
+ sub_halt_bak = !sub_halt; // bit6 : '1' Cancel req.
nmi_count = 0;
reset_fdc();
register_event(this, EVENT_TIMERIRQ_ON, 10000.0 / 4.9152, true, &event_timerirq); // TIMER IRQ
mainmem->reset();
memset(io_w_latch, 0x00, 0x100);
+ sub_busy = (read_signal(SIG_DISPLAY_BUSY) == 0) ? false : true;
//maincpu->reset();
}
{
uint8 backup = irqstat_reg0;
if(flag && !(irqmask_timer)) {
- irqstat_reg0 &= ~0x04;
+ irqstat_reg0 &= 0xfb; //~0x04;
irqstat_timer = true;
if(backup != irqstat_reg0) do_irq();
} else {
uint8 FM7_MAINIO::get_fd04(void)
{
- uint8 val = 0xfc;
- if(display->read_signal(SIG_DISPLAY_BUSY) != 0) val |= 0x80;
+ uint8 val = 0x7c;
+ if(sub_busy) val |= 0x80;
if(!firq_break_key) val |= 0x02;
if(!firq_sub_attention) {
val |= 0x01;
uint8 FM7_MAINIO::get_fd05(void)
{
uint8 val;
- val = (display->read_signal(SIG_DISPLAY_BUSY) != 0) ? 0xfe : 0x7e;
+ val = (sub_busy) ? 0xfe : 0x7e;
if(!extdet_neg) val |= 0x01;
+ //printf("FD05: READ: %d VAL=%02x\n", SDL_GetTicks(), val);
return val;
}
void FM7_MAINIO::set_fd05(uint8 val)
{
- display->write_signal(SIG_FM7_SUB_CANCEL, val, 0x40); // HACK
- display->write_signal(SIG_DISPLAY_HALT, val, 0x80);
+ sub_cancel = ((val & 0x40) != 0) ? true : false;
+ sub_halt = ((val & 0x80) != 0) ? true : false;
+ //display->write_signal(SIG_FM7_SUB_CANCEL, (sub_cancel) ? 0xff : 0x00, 0xff); // HACK
+ //if(sub_halt != sub_halt_bak) display->write_signal(SIG_DISPLAY_HALT, (sub_halt) ? 0xff : 0x00, 0xff); // HACK
+ if(sub_cancel != sub_cancel_bak) {
+ display->write_signal(SIG_FM7_SUB_CANCEL, (sub_cancel) ? 0xff : 0x00, 0xff); // HACK
+ }
+ sub_cancel_bak = sub_cancel;
+ //sub_halt_bak = sub_halt;
#ifdef WITH_Z80
if((val & 0x01) != 0) {
//maincpu->write_signal(SIG_CPU_BUSREQ, 1, 1);
val_b = ((data & mask) != 0);
switch(id) {
+ case FM7_MAINIO_SUB_BUSY:
+ sub_busy = val_b;
+ break;
case FM7_MAINIO_CLOCKMODE: // fd00
if(val_b) {
clock_fast = true;
display->write_signal(SIG_DISPLAY_MODE320, data, 0x40);
break;
case 0x13:
- display->write_signal(SIG_FM7_SUB_BANK, data, 0x07);
+ sub_monitor_type = data & 0x07;
break;
#endif
case 0x15: // OPN CMD
break;
case EVENT_TIMERIRQ_ON:
if(!irqmask_timer) set_irq_timer(true);
- //register_event(this, EVENT_TIMERIRQ_OFF, 10000.0 / (4.9152 * 2.0) , false, NULL); // TIMER IRQ
+ register_event(this, EVENT_TIMERIRQ_OFF, 10000.0 / (4.9152 * 2.0) , false, NULL); // TIMER IRQ
break;
case EVENT_TIMERIRQ_OFF:
if(!irqmask_timer) set_irq_timer(false);
}
// this->write_signal(FM7_MAINIO_CLOCKMODE, clock_fast ? 1 : 0, 1);
}
+
+void FM7_MAINIO::event_vline(int v, int clock)
+{
+ if(sub_halt != sub_halt_bak) {
+ display->write_signal(SIG_DISPLAY_HALT, (sub_halt) ? 0xff : 0x00, 0xff);
+ }
+ sub_halt_bak = sub_halt;
+ //if(firq_sub_attention != firq_sub_attention_bak){
+ // do_firq();
+ //}
+ //firq_sub_attention_bak = firq_sub_attention;
+
+#if defined(_FM77AV_VARIANTS)
+ if(sub_monitor_type != sub_monitor_bak) {
+ display->write_signal(SIG_FM7_SUB_BANK, sub_monitor_type, 0x07);
+ }
+ sub_monitor_bak = sub_monitor_type;
+#endif
+}
+
+
\ No newline at end of file
bool stat_400linemode; // R/W : bit3, '0' = 400line, '1' = 200line.
bool firq_break_key; // bit1, ON = '0'.
bool firq_sub_attention; // bit0, ON = '0'.
+ bool firq_sub_attention_bak; // bit0, ON = '0'.
/* FD04 : W */
bool intmode_fdc; // bit2, '0' = normal, '1' = SFD.
/* FD05 : R */
bool extdet_neg; // bit0 : '1' = none , '0' = exists.
+ bool sub_busy;
/* FD05 : W */
+ bool sub_halt; // bit7 : '1' Halt req.
bool sub_cancel; // bit6 : '1' Cancel req.
+ bool sub_halt_bak; // bit7 : shadow.
+ bool sub_cancel_bak; // bit6 : shadow.
bool z80_sel; // bit0 : '1' = Z80. Maybe only FM-7/77.
/* FD06 : R/W : RS-232C */
bool mode320; // bit6 : true = 320, false = 640
/* FD13 : WO */
uint8 sub_monitor_type; // bit 2 - 0: default = 0.
+ uint8 sub_monitor_bak; // bit 2 - 0: default = 0.
#endif
/* FD15 / FD46 / FD51 : W */
memset(io_w_latch, 0x00, 0x100);
}
~FM7_MAINIO(){}
+ void event_vline(int v, int clock);
+
uint8 opn_regs[4][0x100];
uint32 read_io8(uint32 addr) { // This is only for debug.
addr = addr & 0xfff;
/* macros to access memory */
#define IMMBYTE(b) b = ROP_ARG(PCD); PC++
-#define IMMWORD(w) w.d = (ROP_ARG(PCD) << 8) | ROP_ARG((PCD + 1) & 0xffff); PC += 2
+#define IMMWORD(w) w.b.h = ROP_ARG(PCD) ; w.b.l = ROP_ARG((PCD + 1) & 0xffff); PC += 2
#define PUSHBYTE(b) --S; WM(SD,b)
#define PUSHWORD(w) --S; WM(SD, w.b.l); --S; WM(SD, w.b.h)
tmpea.d = 0; \
tmpea.b.h = DP; \
IMMBYTE(tmpea.b.l); \
- EAP = tmpea; }
+ EAD = tmpea.w.l; }
#define IMM8 EAD = PCD; PC++
#define IMM16 EAD = PCD; PC += 2
/* macros for branch instructions */
inline void MC6809::BRANCH(bool cond)
{
- uint8 t;
+ volatile uint8 t;
IMMBYTE(t);
if(!cond) return;
- //if(t >= 0x80) {
- // PC = PC - 0x0100 + t;
- //} else {
- // PC = PC + t;
- //}
- PC = PC + SIGNED(t);
+ if(t >= 0x80) {
+ PC = PC - 0x0100 + t;
+ } else {
+ PC = PC + t;
+ }
+ //PC = PC + SIGNED(t);
PC = PC & 0xffff;
}
if(d_debugger->now_suspended) {
emu->mute_sound();
while(d_debugger->now_debugging && d_debugger->now_suspended) {
- Sleep(10);
+ Sleep(10);
}
}
if(d_debugger->now_debugging) {
/* $aD JSR indexed ----- */
OP_HANDLER(jsr_ix) {
- fetch_effective_address();
- PUSHWORD(pPC);
- PCD = EAD;
- }
+ fetch_effective_address();
+ PUSHWORD(pPC);
+ PCD = EAD;
+}
/* $aE LDX (LDY) indexed -**0- */
OP_HANDLER(ldx_ix) {
pair dp; /* Direct Page register (page in MSB) */
pair u, s; /* Stack pointers */
pair x, y; /* Index registers */
- volatile uint8 cc;
+ uint8 cc;
pair ea; /* effective address */
uint8 int_state;