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drm/amd/pp: update smu_version value for CI/VI
authorRex Zhu <Rex.Zhu@amd.com>
Tue, 19 Dec 2017 06:07:09 +0000 (14:07 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 20 Dec 2017 16:57:14 +0000 (11:57 -0500)
Set the new common smu firmware version for smu7 parts (CI and VI).

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c

index c6c741a..0b4a556 100644 (file)
@@ -2316,6 +2316,7 @@ static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
        cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
 
        hwmgr->is_kicker = info.is_kicker;
+       hwmgr->smu_version = info.version;
        byte_count = info.image_size;
        src = (uint8_t *)info.kptr;
        start_addr = info.ucode_start_address;
index d75bb99..1253126 100644 (file)
@@ -204,7 +204,7 @@ static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
                pr_err("[ powerplay ] SMC address is beyond the SMC RAM area\n");
                return -EINVAL;
        }
-
+       hwmgr->smu_version = info.version;
        /* wait for smc boot up */
        PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
                                         RCU_UC_EVENTS, boot_seq_done, 0);
index 7f5359a..cb95e88 100644 (file)
@@ -535,7 +535,7 @@ int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
                        smu7_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info);
 
        hwmgr->is_kicker = info.is_kicker;
-
+       hwmgr->smu_version = info.version;
        result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
 
        return result;