drm/i915/xelpd: Support DP1.4 compression BPPs

Support compression BPPs from bpc to uncompressed BPP -1.
So far we have 8,10,12 as valid compressed BPPS now the
support is extended.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-5-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9f699d3..6f7bc9b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -109,6 +109,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp)
 }
 
 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
+static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc);
 
 /* update sink rates from dpcd */
 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
@@ -494,7 +495,8 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915)
 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
                                       u32 link_clock, u32 lane_count,
                                       u32 mode_clock, u32 mode_hdisplay,
-                                      bool bigjoiner)
+                                      bool bigjoiner,
+                                      u32 pipe_bpp)
 {
        u32 bits_per_pixel, max_bpp_small_joiner_ram;
        int i;
@@ -541,12 +543,17 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
                return 0;
        }
 
-       /* Find the nearest match in the array of known BPPs from VESA */
-       for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
-               if (bits_per_pixel < valid_dsc_bpp[i + 1])
-                       break;
+       /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
+       if (DISPLAY_VER(i915) >= 13) {
+               bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
+       } else {
+               /* Find the nearest match in the array of known BPPs from VESA */
+               for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
+                       if (bits_per_pixel < valid_dsc_bpp[i + 1])
+                               break;
+               }
+               bits_per_pixel = valid_dsc_bpp[i];
        }
-       bits_per_pixel = valid_dsc_bpp[i];
 
        /*
         * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
@@ -780,6 +787,12 @@ intel_dp_mode_valid(struct drm_connector *connector,
         */
        if (DISPLAY_VER(dev_priv) >= 10 &&
            drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
+               /*
+                * TBD pass the connector BPC,
+                * for now U8_MAX so that max BPC on that platform would be picked
+                */
+               int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX);
+
                if (intel_dp_is_edp(intel_dp)) {
                        dsc_max_output_bpp =
                                drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
@@ -793,7 +806,8 @@ intel_dp_mode_valid(struct drm_connector *connector,
                                                            max_lanes,
                                                            target_clock,
                                                            mode->hdisplay,
-                                                           bigjoiner) >> 4;
+                                                           bigjoiner,
+                                                           pipe_bpp) >> 4;
                        dsc_slice_count =
                                intel_dp_dsc_get_slice_count(intel_dp,
                                                             target_clock,
@@ -1240,7 +1254,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
                                                    pipe_config->lane_count,
                                                    adjusted_mode->crtc_clock,
                                                    adjusted_mode->crtc_hdisplay,
-                                                   pipe_config->bigjoiner);
+                                                   pipe_config->bigjoiner,
+                                                   pipe_bpp);
                dsc_dp_slice_count =
                        intel_dp_dsc_get_slice_count(intel_dp,
                                                     adjusted_mode->crtc_clock,