drm/i915/gen9: h/w w/a: syncing dependencies between camera and graphics

This one doesn't have one of these nice cryptic names unfortunately.

v2: Added missing register bitmap

Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd3430f..dab4c1e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6213,6 +6213,7 @@ enum skl_disp_power_wells {
 #define HALF_SLICE_CHICKEN3            0xe184
 #define   HSW_SAMPLE_C_PERFORMANCE     (1<<9)
 #define   GEN8_CENTROID_PIXEL_OPT_DIS  (1<<8)
+#define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC  (1<<5)
 #define   GEN8_SAMPLER_POWER_BYPASS_DIS        (1<<1)
 
 /* Audio */

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 248db51..909430f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -882,6 +882,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
        WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
                          PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
+       /* Syncing dependencies between camera and graphics */
+       WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
+                         GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
+
        if (INTEL_REVID(dev) == SKL_REVID_A0) {
                /*
                * WaDisableDgMirrorFixInHalfSliceChicken5:skl