media: ti-vpe: cal: print errors on timeouts

The driver does not print any errors on ComplexIO reset timeout or when
waiting for stop-state, making it difficult to debug and notice
problems.

Add error prints for these cases.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c
index 838215a..9bfe83f 100644 (file)
--- a/drivers/media/platform/ti-vpe/cal.c
+++ b/drivers/media/platform/ti-vpe/cal.c
@@ -839,10 +839,11 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx)
                        break;
                usleep_range(1000, 1100);
        }
-       ctx_dbg(3, ctx, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO Reset Done (%d) %s\n",
-               ctx->csi2_port,
-               reg_read(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port)), i,
-               (i >= 250) ? "(timeout)" : "");
+
+       if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),
+                          CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) !=
+                          CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED)
+               ctx_err(ctx, "Timeout waiting for Complex IO reset done\n");
 
        /* 4. G. Wait for all enabled lane to reach stop state */
        for (i = 0; i < 10; i++) {
@@ -853,10 +854,10 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx)
                        break;
                usleep_range(1000, 1100);
        }
-       ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Stop State Reached %s\n",
-               ctx->csi2_port,
-               reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port)),
-               (i >= 10) ? "(timeout)" : "");
+
+       if (reg_read_field(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port),
+                          CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0)
+               ctx_err(ctx, "Timeout waiting for stop state\n");
 
        ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x (Bit(31,28) should be set!)\n",
                (ctx->csi2_port - 1), reg_read(ctx->cc, CAL_CSI2_PHY_REG1));