# Conditional Branches
####
-bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=%assemble_12
-bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=%assemble_12
+bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
+bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=%assemble_12
movb 110010 ..... ..... ... ........... . . @rrb_cf f=0
movbi 110011 ..... ..... ... ........... . . @rib_cf f=0
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
- bool d = false;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- if (cond_need_ext(ctx, d)) {
+ if (cond_need_ext(ctx, a->d)) {
/* Force shift into [32,63] */
tcg_gen_ori_reg(tmp, cpu_sar, 32);
tcg_gen_shl_reg(tmp, tcg_r, tmp);
{
TCGv_reg tmp, tcg_r;
DisasCond cond;
- bool d = false;
int p;
nullify_over(ctx);
tmp = tcg_temp_new();
tcg_r = load_gpr(ctx, a->r);
- p = a->p | (cond_need_ext(ctx, d) ? 32 : 0);
+ p = a->p | (cond_need_ext(ctx, a->d) ? 32 : 0);
tcg_gen_shli_reg(tmp, tcg_r, p);
cond = cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp);