if (priv->tx_pwr_data_read_from_eeprom) {
dwArrayLen = RTL8192E_MACPHY_ARR_PG_LEN;
- pdwArray = Rtl819XMACPHY_Array_PG;
+ pdwArray = RTL8192E_MACPHY_ARR_PG;
} else {
dwArrayLen = RTL8192E_MACPHY_ARR_LEN;
#define MAX_DOZE_WAITING_TIMES_9x 64
-#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
0x318, 0x00000fff, 0x00000100,
};
-u32 Rtl8192PciEMACPHY_Array_PG[] = {
+u32 RTL8192E_MACPHY_ARR_PG[] = {
0x03c, 0xffff0000, 0x00000f0f,
0xe00, 0xffffffff, 0x06090909,
0xe04, 0xffffffff, 0x00030306,
#define RTL8192E_MACPHY_ARR_LEN 18
extern u32 Rtl8192PciEMACPHY_Array[RTL8192E_MACPHY_ARR_LEN];
#define RTL8192E_MACPHY_ARR_PG_LEN 30
-extern u32 Rtl8192PciEMACPHY_Array_PG[RTL8192E_MACPHY_ARR_PG_LEN];
+extern u32 RTL8192E_MACPHY_ARR_PG[RTL8192E_MACPHY_ARR_PG_LEN];
#define RTL8192E_AGCTAB_ARR_LEN 384
extern u32 Rtl8192PciEAGCTAB_Array[RTL8192E_AGCTAB_ARR_LEN];