binutils/

2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	* dwarf.c (dwarf_regnames_i386): Remove AVX registers.
	(dwarf_regnames_x86_64): Likewise.

gas/testsuite/

2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/cfi/cfi-i386.s: Remove tests for AVX register maps.
	* gas/cfi/cfi-x86_64.s: Likewise.

	* gas/cfi/cfi-i386.d: Updated.
	* gas/cfi/cfi-x86_64.d: Likewise.

opcodes/

2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-reg.tbl: Use Dw2Inval on AVX registers.
	* i386-tbl.h: Regenerated.

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index d4e71ae..fd4ac13 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * dwarf.c (dwarf_regnames_i386): Remove AVX registers.
+       (dwarf_regnames_x86_64): Likewise.
+
 2008-07-30  Alan Modra  <amodra@bigpond.net.au>
 
        * dlltool.c, dwarf.c, objdump.c, readelf.c, resrc.c, resres.c,

diff --git a/binutils/dwarf.c b/binutils/dwarf.c
index 26ab941..3a5ef0f 100644 (file)
--- a/binutils/dwarf.c
+++ b/binutils/dwarf.c
@@ -3616,10 +3616,7 @@ static const char *const dwarf_regnames_i386[] =
   "mm4", "mm5", "mm6", "mm7",
   "fcw", "fsw", "mxcsr",
   "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
-  "tr", "ldtr",
-  NULL, NULL, NULL,
-  "ymm0", "ymm1", "ymm2", "ymm3",
-  "ymm4", "ymm5", "ymm6", "ymm7"
+  "tr", "ldtr"
 };
 
 static const char *const dwarf_regnames_x86_64[] =
@@ -3641,12 +3638,7 @@ static const char *const dwarf_regnames_x86_64[] =
   "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
   "fs.base", "gs.base", NULL, NULL,
   "tr", "ldtr",
-  "mxcsr", "fcw", "fsw",
-  NULL, NULL, NULL,
-  "ymm0", "ymm1", "ymm2", "ymm3",
-  "ymm4", "ymm5", "ymm6", "ymm7",
-  "ymm8", "ymm9", "ymm10", "ymm11",
-  "ymm12", "ymm13", "ymm14", "ymm15"
+  "mxcsr", "fcw", "fsw"
 };
 
 static const char *const *dwarf_regnames;

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 7c43370..1ea3df5 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * gas/cfi/cfi-i386.s: Remove tests for AVX register maps.
+       * gas/cfi/cfi-x86_64.s: Likewise.
+
+       * gas/cfi/cfi-i386.d: Updated.
+       * gas/cfi/cfi-x86_64.d: Likewise.
+
 2008-07-31  Peter Bergner  <bergner@vnet.ibm.com>
 
        * gas/ppc/cell.s: Add altivec instructions.

diff --git a/gas/testsuite/gas/cfi/cfi-i386.d b/gas/testsuite/gas/cfi/cfi-i386.d
index 38470da..ef477d3 100644 (file)
--- a/gas/testsuite/gas/cfi/cfi-i386.d
+++ b/gas/testsuite/gas/cfi/cfi-i386.d
@@ -57,7 +57,7 @@ The section .eh_frame contains:
   DW_CFA_undefined: r8 \(eip\)
   DW_CFA_nop
 
-000000a0 000000ac 00000018 FDE cie=0000008c pc=00000044..00000079
+000000a0 00000094 00000018 FDE cie=0000008c pc=00000044..00000071
   DW_CFA_advance_loc: 1 to 00000045
   DW_CFA_undefined: r0 \(eax\)
   DW_CFA_advance_loc: 1 to 00000046
@@ -146,24 +146,7 @@ The section .eh_frame contains:
   DW_CFA_undefined: r35 \(mm6\)
   DW_CFA_advance_loc: 1 to 00000070
   DW_CFA_undefined: r36 \(mm7\)
-  DW_CFA_advance_loc: 1 to 00000071
-  DW_CFA_undefined: r53 \(ymm0\)
-  DW_CFA_advance_loc: 1 to 00000072
-  DW_CFA_undefined: r54 \(ymm1\)
-  DW_CFA_advance_loc: 1 to 00000073
-  DW_CFA_undefined: r55 \(ymm2\)
-  DW_CFA_advance_loc: 1 to 00000074
-  DW_CFA_undefined: r56 \(ymm3\)
-  DW_CFA_advance_loc: 1 to 00000075
-  DW_CFA_undefined: r57 \(ymm4\)
-  DW_CFA_advance_loc: 1 to 00000076
-  DW_CFA_undefined: r58 \(ymm5\)
-  DW_CFA_advance_loc: 1 to 00000077
-  DW_CFA_undefined: r59 \(ymm6\)
-  DW_CFA_advance_loc: 1 to 00000078
-  DW_CFA_undefined: r60 \(ymm7\)
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop
 
-#pass

diff --git a/gas/testsuite/gas/cfi/cfi-i386.s b/gas/testsuite/gas/cfi/cfi-i386.s
index 29119db..9da0db1 100644 (file)
--- a/gas/testsuite/gas/cfi/cfi-i386.s
+++ b/gas/testsuite/gas/cfi/cfi-i386.s
@@ -162,13 +162,4 @@ func_all_registers:
        .cfi_undefined mm6      ; nop
        .cfi_undefined mm7      ; nop
 
-       .cfi_undefined ymm0     ; nop
-       .cfi_undefined ymm1     ; nop
-       .cfi_undefined ymm2     ; nop
-       .cfi_undefined ymm3     ; nop
-       .cfi_undefined ymm4     ; nop
-       .cfi_undefined ymm5     ; nop
-       .cfi_undefined ymm6     ; nop
-       .cfi_undefined ymm7     ; nop
-
        .cfi_endproc

diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.d b/gas/testsuite/gas/cfi/cfi-x86_64.d
index 0f6566b..3fc7d53 100644 (file)
--- a/gas/testsuite/gas/cfi/cfi-x86_64.d
+++ b/gas/testsuite/gas/cfi/cfi-x86_64.d
@@ -94,7 +94,7 @@ The section .eh_frame contains:
   DW_CFA_undefined: r16 \(rip\)
   DW_CFA_nop
 
-000000e8 000000fc 00000018 FDE cie=000000d4 pc=00000058..000000a7
+000000e8 000000cc 00000018 FDE cie=000000d4 pc=00000058..00000097
   DW_CFA_advance_loc: 1 to 00000059
   DW_CFA_undefined: r0 \(rax\)
   DW_CFA_advance_loc: 1 to 0000005a
@@ -219,42 +219,9 @@ The section .eh_frame contains:
   DW_CFA_undefined: r47 \(mm6\)
   DW_CFA_advance_loc: 1 to 00000096
   DW_CFA_undefined: r48 \(mm7\)
-  DW_CFA_advance_loc: 1 to 00000097
-  DW_CFA_undefined: r70 \(ymm0\)
-  DW_CFA_advance_loc: 1 to 00000098
-  DW_CFA_undefined: r71 \(ymm1\)
-  DW_CFA_advance_loc: 1 to 00000099
-  DW_CFA_undefined: r72 \(ymm2\)
-  DW_CFA_advance_loc: 1 to 0000009a
-  DW_CFA_undefined: r73 \(ymm3\)
-  DW_CFA_advance_loc: 1 to 0000009b
-  DW_CFA_undefined: r74 \(ymm4\)
-  DW_CFA_advance_loc: 1 to 0000009c
-  DW_CFA_undefined: r75 \(ymm5\)
-  DW_CFA_advance_loc: 1 to 0000009d
-  DW_CFA_undefined: r76 \(ymm6\)
-  DW_CFA_advance_loc: 1 to 0000009e
-  DW_CFA_undefined: r77 \(ymm7\)
-  DW_CFA_advance_loc: 1 to 0000009f
-  DW_CFA_undefined: r78 \(ymm8\)
-  DW_CFA_advance_loc: 1 to 000000a0
-  DW_CFA_undefined: r79 \(ymm9\)
-  DW_CFA_advance_loc: 1 to 000000a1
-  DW_CFA_undefined: r80 \(ymm10\)
-  DW_CFA_advance_loc: 1 to 000000a2
-  DW_CFA_undefined: r81 \(ymm11\)
-  DW_CFA_advance_loc: 1 to 000000a3
-  DW_CFA_undefined: r82 \(ymm12\)
-  DW_CFA_advance_loc: 1 to 000000a4
-  DW_CFA_undefined: r83 \(ymm13\)
-  DW_CFA_advance_loc: 1 to 000000a5
-  DW_CFA_undefined: r84 \(ymm14\)
-  DW_CFA_advance_loc: 1 to 000000a6
-  DW_CFA_undefined: r85 \(ymm15\)
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop
   DW_CFA_nop
 
-#pass

diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.s b/gas/testsuite/gas/cfi/cfi-x86_64.s
index 4fbc4e1..65c2aa2 100644 (file)
--- a/gas/testsuite/gas/cfi/cfi-x86_64.s
+++ b/gas/testsuite/gas/cfi/cfi-x86_64.s
@@ -211,21 +211,4 @@ func_all_registers:
        .cfi_undefined mm6      ; nop
        .cfi_undefined mm7      ; nop
 
-       .cfi_undefined ymm0     ; nop
-       .cfi_undefined ymm1     ; nop
-       .cfi_undefined ymm2     ; nop
-       .cfi_undefined ymm3     ; nop
-       .cfi_undefined ymm4     ; nop
-       .cfi_undefined ymm5     ; nop
-       .cfi_undefined ymm6     ; nop
-       .cfi_undefined ymm7     ; nop
-       .cfi_undefined ymm8     ; nop
-       .cfi_undefined ymm9     ; nop
-       .cfi_undefined ymm10    ; nop
-       .cfi_undefined ymm11    ; nop
-       .cfi_undefined ymm12    ; nop
-       .cfi_undefined ymm13    ; nop
-       .cfi_undefined ymm14    ; nop
-       .cfi_undefined ymm15    ; nop
-
        .cfi_endproc

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4b73185..22d20b3 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2008-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-reg.tbl: Use Dw2Inval on AVX registers.
+       * i386-tbl.h: Regenerated.
+
 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 
        * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.

diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index c88a9e0..d1885e1 100644 (file)
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -189,22 +189,22 @@ xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
 xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
 xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
 // AVX registers.
-ymm0, RegYMM, 0, 0, 53, 70
-ymm1, RegYMM, 0, 1, 54, 71
-ymm2, RegYMM, 0, 2, 55, 72
-ymm3, RegYMM, 0, 3, 56, 73
-ymm4, RegYMM, 0, 4, 57, 74
-ymm5, RegYMM, 0, 5, 58, 75
-ymm6, RegYMM, 0, 6, 59, 76
-ymm7, RegYMM, 0, 7, 60, 77
-ymm8, RegYMM, RegRex, 0, Dw2Inval, 78
-ymm9, RegYMM, RegRex, 1, Dw2Inval, 79
-ymm10, RegYMM, RegRex, 2, Dw2Inval, 80
-ymm11, RegYMM, RegRex, 3, Dw2Inval, 81
-ymm12, RegYMM, RegRex, 4, Dw2Inval, 82
-ymm13, RegYMM, RegRex, 5, Dw2Inval, 83
-ymm14, RegYMM, RegRex, 6, Dw2Inval, 84
-ymm15, RegYMM, RegRex, 7, Dw2Inval, 85
+ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
+ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
+ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
+ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
+ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
+ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
+ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
+ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
+ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
+ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
+ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
+ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
+ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
+ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
+ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
+ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
 // No type will make these registers rejected for all purposes except
 // for addressing.  This saves creating one extra type for RIP/EIP.
 rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index ad1e331..6f0b165 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -31840,82 +31840,82 @@ const reg_entry i386_regtab[] =
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    0, 0, { 53, 70 } },
+    0, 0, { Dw2Inval, Dw2Inval } },
   { "ymm1",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    0, 1, { 54, 71 } },
+    0, 1, { Dw2Inval, Dw2Inval } },
   { "ymm2",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    0, 2, { 55, 72 } },
+    0, 2, { Dw2Inval, Dw2Inval } },
   { "ymm3",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    0, 3, { 56, 73 } },
+    0, 3, { Dw2Inval, Dw2Inval } },
   { "ymm4",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    0, 4, { 57, 74 } },
+    0, 4, { Dw2Inval, Dw2Inval } },
   { "ymm5",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    0, 5, { 58, 75 } },
+    0, 5, { Dw2Inval, Dw2Inval } },
   { "ymm6",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    0, 6, { 59, 76 } },
+    0, 6, { Dw2Inval, Dw2Inval } },
   { "ymm7",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    0, 7, { 60, 77 } },
+    0, 7, { Dw2Inval, Dw2Inval } },
   { "ymm8",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    RegRex, 0, { Dw2Inval, 78 } },
+    RegRex, 0, { Dw2Inval, Dw2Inval } },
   { "ymm9",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    RegRex, 1, { Dw2Inval, 79 } },
+    RegRex, 1, { Dw2Inval, Dw2Inval } },
   { "ymm10",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    RegRex, 2, { Dw2Inval, 80 } },
+    RegRex, 2, { Dw2Inval, Dw2Inval } },
   { "ymm11",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    RegRex, 3, { Dw2Inval, 81 } },
+    RegRex, 3, { Dw2Inval, Dw2Inval } },
   { "ymm12",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    RegRex, 4, { Dw2Inval, 82 } },
+    RegRex, 4, { Dw2Inval, Dw2Inval } },
   { "ymm13",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    RegRex, 5, { Dw2Inval, 83 } },
+    RegRex, 5, { Dw2Inval, Dw2Inval } },
   { "ymm14",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    RegRex, 6, { Dw2Inval, 84 } },
+    RegRex, 6, { Dw2Inval, Dw2Inval } },
   { "ymm15",
     { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0 } },
-    RegRex, 7, { Dw2Inval, 85 } },
+    RegRex, 7, { Dw2Inval, Dw2Inval } },
   { "rip",
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
        0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,