msm: pcie: add PCIe support for 3.18 kernel

Add PCIe support for 3.18 kernel. Added enumeration,
interrupts, and hardware configurations support for
PCIe.

Signed-off-by: Tony Truong <truong@codeaurora.org>

diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt
index 09a3090..cee73db 100644 (file)
--- a/Documentation/devicetree/bindings/pci/msm_pcie.txt
+++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt
@@ -84,6 +84,8 @@ Optional Properties:
   - qcom,smmu-exist: PCIe uses a SMMU.
   - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become
     stable after power on, before de-assert the PERST to the endpoint.
+  - linux,pci-domain: For details of pci-domains properties, please refer to:
+    "Documentation/devicetree/bindings/pci/pci.txt"
   - qcom,tlp-rd-size: The max TLP read size (Calculation: 128 times 2 to the
     tlp-rd-size power).
   - Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for

diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
index 14d0723..4c9a6eb 100644 (file)
--- a/drivers/pci/host/pci-msm.c
+++ b/drivers/pci/host/pci-msm.c
@@ -22,6 +22,7 @@
 #include <linux/gpio.h>
 #include <linux/iopoll.h>
 #include <linux/kernel.h>
+#include <linux/of_pci.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
@@ -4044,29 +4045,39 @@ int msm_pcie_enumerate(u32 rc_idx)
                /* kick start ARM PCI configuration framework */
                if (!ret) {
                        struct pci_dev *pcidev = NULL;
-                       struct pci_host_bridge *bridge;
-                       resource_size_t lastbus;
                        bool found = false;
+                       struct pci_bus *bus;
+                       resource_size_t iobase = 0;
                        u32 ids = readl_relaxed(msm_pcie_dev[rc_idx].dm_core);
                        u32 vendor_id = ids & 0xffff;
                        u32 device_id = (ids & 0xffff0000) >> 16;
+                       LIST_HEAD(res);
 
                        PCIE_DBG(dev, "vendor-id:0x%x device_id:0x%x\n",
                                        vendor_id, device_id);
 
-                       bridge = of_create_pci_host_bridge(&dev->pdev->dev,
-                                                       &msm_pcie_ops,
-                                                       dev);
+                       ret = of_pci_get_host_bridge_resources(
+                                               dev->pdev->dev.of_node,
+                                               0, 0xff, &res, &iobase);
+                       if (ret) {
+                               PCIE_ERR(dev,
+                                       "PCIe: failed to get host bridge resources for RC%d: %d\n",
+                                       dev->rc_idx, ret);
+
+                               return ret;
+                       }
 
-                       if (IS_ERR_OR_NULL(bridge))
-                               return PTR_ERR(bridge);
+                       bus = pci_create_root_bus(&dev->pdev->dev, 0,
+                                               &msm_pcie_ops, dev, &res);
+                       if (!bus) {
+                               PCIE_ERR(dev,
+                                       "PCIe: failed to create root bus for RC%d\n",
+                                       dev->rc_idx);
 
-                       pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
-                       pci_add_flags(PCI_REASSIGN_ALL_BUS |
-                                       PCI_REASSIGN_ALL_RSRC);
+                               return -ENOMEM;
+                       }
 
-                       lastbus = pci_rescan_bus(bridge->bus);
-                       pci_bus_update_busn_res_end(bridge->bus, lastbus);
+                       pci_rescan_bus(bus);
 
                        dev->enumerated = true;
 
@@ -4534,7 +4545,7 @@ void msm_pcie_destroy_irq(unsigned int irq, struct msm_pcie_dev_t *pcie_dev)
        PCIE_DBG(dev, "RC%d\n", dev->rc_idx);
 
        if (!dev->msi_gicm_addr)
-               dynamic_irq_cleanup(irq);
+               irq_dispose_mapping(irq);
 
        PCIE_DBG(dev, "Before clear_bit pos:%d msi_irq_in_use:%ld\n",
                pos, *dev->msi_irq_in_use);