[X86] Add MOV16ri*/MOV32ri*/MOV64ri* to scheduler models to match MOV8ri. Correct...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327872 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td
index bf70832..b8a40b4 100644 (file)
--- a/lib/Target/X86/X86InstrCompiler.td
+++ b/lib/Target/X86/X86InstrCompiler.td
@@ -318,9 +318,9 @@ def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",
 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
 // that would make it more difficult to rematerialize.
 let isReMaterializable = 1, isAsCheapAsAMove = 1,
-    isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteALU] in
+    isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in
 def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", [],
-                  IIC_ALU_NONMEM>;
+                  IIC_MOV>;
 
 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
 // actually the zero-extension of a 32-bit constant and for labels in the

diff --git a/lib/Target/X86/X86SchedBroadwell.td b/lib/Target/X86/X86SchedBroadwell.td
index 77e595b..856e5c6 100755 (executable)
--- a/lib/Target/X86/X86SchedBroadwell.td
+++ b/lib/Target/X86/X86SchedBroadwell.td
@@ -816,7 +816,7 @@ def: InstRW<[BWWriteResGroup9], (instregex "DEC(8|16|32|64)r")>;
 def: InstRW<[BWWriteResGroup9], (instregex "INC(8|16|32|64)r")>;
 def: InstRW<[BWWriteResGroup9], (instregex "LAHF")>;
 def: InstRW<[BWWriteResGroup9], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[BWWriteResGroup9], (instregex "MOV8ri")>;
+def: InstRW<[BWWriteResGroup9], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr16")>;
 def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr32")>;
 def: InstRW<[BWWriteResGroup9], (instregex "MOVSX(16|32|64)rr8")>;

diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td
index 8813e1f..e2559a4 100644 (file)
--- a/lib/Target/X86/X86SchedHaswell.td
+++ b/lib/Target/X86/X86SchedHaswell.td
@@ -598,9 +598,8 @@ def HWWriteResGroup0_2 : SchedWriteRes<[HWPort23]> {
 def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVD64rm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVD64to64rm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MMX_MOVQ64rm")>;
-def: InstRW<[HWWriteResGroup0_2], (instregex "MOV(16|32|64)rm")>;
+def: InstRW<[HWWriteResGroup0_2], (instregex "MOV(8|16|32|64)rm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MOV64toPQIrm")>;
-def: InstRW<[HWWriteResGroup0_2], (instregex "MOV8rm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MOVDDUPrm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MOVDI2PDIrm")>;
 def: InstRW<[HWWriteResGroup0_2], (instregex "MOVQI2PQIrm")>;
@@ -1233,7 +1232,7 @@ def: InstRW<[HWWriteResGroup10], (instregex "DEC(8|16|32|64)r")>;
 def: InstRW<[HWWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
 def: InstRW<[HWWriteResGroup10], (instregex "LAHF")>;
 def: InstRW<[HWWriteResGroup10], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[HWWriteResGroup10], (instregex "MOV8ri")>;
+def: InstRW<[HWWriteResGroup10], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
 def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
 def: InstRW<[HWWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;

diff --git a/lib/Target/X86/X86SchedSandyBridge.td b/lib/Target/X86/X86SchedSandyBridge.td
index ee2d2c0..a8372e7 100644 (file)
--- a/lib/Target/X86/X86SchedSandyBridge.td
+++ b/lib/Target/X86/X86SchedSandyBridge.td
@@ -626,7 +626,7 @@ def: InstRW<[SBWriteResGroup6], (instregex "INC(8|16|32|64)r")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[SBWriteResGroup6], (instregex "MOV8ri")>;
+def: InstRW<[SBWriteResGroup6], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQArr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MOVDQUrr")>;
 def: InstRW<[SBWriteResGroup6], (instregex "MOVPQI2QIrr")>;

diff --git a/lib/Target/X86/X86SchedSkylakeClient.td b/lib/Target/X86/X86SchedSkylakeClient.td
index 23ef6bf..1891f13 100644 (file)
--- a/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/lib/Target/X86/X86SchedSkylakeClient.td
@@ -822,7 +822,7 @@ def: InstRW<[SKLWriteResGroup10], (instregex "DEC(8|16|32|64)r")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "LAHF")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[SKLWriteResGroup10], (instregex "MOV8ri")>;
+def: InstRW<[SKLWriteResGroup10], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
 def: InstRW<[SKLWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;

diff --git a/lib/Target/X86/X86SchedSkylakeServer.td b/lib/Target/X86/X86SchedSkylakeServer.td
index aa1ed43..42de233 100755 (executable)
--- a/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/lib/Target/X86/X86SchedSkylakeServer.td
@@ -1252,7 +1252,7 @@ def: InstRW<[SKXWriteResGroup10], (instregex "DEC(8|16|32|64)r")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "INC(8|16|32|64)r")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "LAHF")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "MOV(8|16|32|64)rr")>;
-def: InstRW<[SKXWriteResGroup10], (instregex "MOV8ri")>;
+def: InstRW<[SKXWriteResGroup10], (instregex "MOV(8|16|32|64)ri")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr16")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr32")>;
 def: InstRW<[SKXWriteResGroup10], (instregex "MOVSX(16|32|64)rr8")>;