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ASoC: wm8960: Fix PLL register writes
author
Mike Dyer
<mike.dyer@md-soft.co.uk>
Fri, 16 Aug 2013 17:36:28 +0000
(18:36 +0100)
committer
Mark Brown
<broonie@linaro.org>
Sun, 18 Aug 2013 15:30:26 +0000
(16:30 +0100)
Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part
should be split across each register in 8bit chunks.
Signed-off-by: Mike Dyer <mike.dyer@md-soft.co.uk>
Signed-off-by: Mark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org
sound/soc/codecs/wm8960.c
patch
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diff --git
a/sound/soc/codecs/wm8960.c
b/sound/soc/codecs/wm8960.c
index
0a4ffdd
..
5e5af89
100644
(file)
--- a/
sound/soc/codecs/wm8960.c
+++ b/
sound/soc/codecs/wm8960.c
@@
-857,9
+857,9
@@
static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
if (pll_div.k) {
reg |= 0x20;
- snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 1
8) & 0x3
f);
- snd_soc_write(codec, WM8960_PLL3, (pll_div.k >>
9) & 0x1
ff);
- snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x
1
ff);
+ snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 1
6) & 0xf
f);
+ snd_soc_write(codec, WM8960_PLL3, (pll_div.k >>
8) & 0x
ff);
+ snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
}
snd_soc_write(codec, WM8960_PLL1, reg);