drm/amdgpu/VCN2.0: remove powergating for UVDW tile

No UVDW tile any more from VCN2.0, so mark out related fields.

It fixes error:
"[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa"

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 3f6349c..7ae7280 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -68,6 +68,7 @@
 
 enum engine_status_constants {
        UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
+       UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
        UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002,
        UVD_STATUS__UVD_BUSY = 0x00000004,
        GB_ADDR_CONFIG_DEFAULT = 0x26010011,

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 04cac0b..729d323 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -698,12 +698,11 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
                        | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
                        | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
                        | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
-                       | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
-                       | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
+                       | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
 
                WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
                SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS,
-                       UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret);
+                       UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF, ret);
        } else {
                data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
                        | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
@@ -714,10 +713,9 @@ static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev)
                        | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
                        | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
                        | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
-                       | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
-                       | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
+                       | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
                WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
-               SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF, ret);
+               SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFF, ret);
        }
 
        /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS,
@@ -754,8 +752,7 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
                        | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
                        | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
                        | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
-                       | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
-                       | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
+                       | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT);
 
                WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 
@@ -768,9 +765,8 @@ static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev)
                        | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
                        | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
                        | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
-                       | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
-                       | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
-               SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret);
+                       | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT);
+               SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF, ret);
        }
 }