; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=corei7-avx | FileCheck %s
-define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp {
+define void @wideloads(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind {
; CHECK-LABEL: wideloads:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %xmm0
ret void
}
-define void @widestores(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind uwtable noinline ssp {
+define void @widestores(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind {
; CHECK-LABEL: widestores:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovaps (%rdi), %ymm0
ret void
}
+define void @widestores_unaligned_load(<8 x float>* %a, <8 x float>* %b, <8 x float>* %c) nounwind {
+; CHECK-LABEL: widestores_unaligned_load:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vmovaps (%rdi), %ymm0
+; CHECK-NEXT: vmovaps (%rsi), %xmm1
+; CHECK-NEXT: vmovaps 16(%rsi), %xmm2
+; CHECK-NEXT: vmovaps %ymm0, (%rsi)
+; CHECK-NEXT: vmovaps %xmm2, 16(%rdi)
+; CHECK-NEXT: vmovaps %xmm1, (%rdi)
+; CHECK-NEXT: vzeroupper
+; CHECK-NEXT: retq
+ %v0 = load <8 x float>, <8 x float>* %a, align 32 ; <--- aligned
+ %v1 = load <8 x float>, <8 x float>* %b, align 16 ; <--- unaligned
+ store <8 x float> %v0, <8 x float>* %b, align 32 ; <--- aligned
+ store <8 x float> %v1, <8 x float>* %a, align 16 ; <--- unaligned
+ ret void
+}