drm/i915: Fix GEN8_MISCCPCTL

Register 0x9424 is not replicated on any platform, so it shouldn't be
declared with REG_MCR(). Declaring it with _MMIO() is basically
duplicate of the GEN7 version, so just remove the GEN8 and change all
the callers to use the right functions.

Old versions of the gen8 bspec page used to contain a table with MCR
registers, apparently implying 0x9400 - 0x94ff registers were
replicated. However that table went away and there is no information
related to the ranges for gen8 anymore. Moreover the current behavior of
the driver wouldn't do anything special for 0x9424 since there is no
equivalent table in intel_gt_mcr.c: the driver would just fallback to
intel_uncore_{read,write}(). Therefore, do not care about the possible
special case for gen8 and just use the register as non-MCR for all the
platforms.

One place doing read + write is also converted to intel_uncore_rmw().

v2: Reword commit message adding the justification wrt gen8

Fixes: a9e69428b1b4 ("drm/i915: Define MCR registers explicitly")
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230206165410.3056073-1-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 928698c..be0f6e3 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -686,10 +686,7 @@
 #define GEN6_RSTCTL                            _MMIO(0x9420)
 
 #define GEN7_MISCCPCTL                         _MMIO(0x9424)
-#define   GEN7_DOP_CLOCK_GATE_ENABLE           (1 << 0)
-
-#define GEN8_MISCCPCTL                         MCR_REG(0x9424)
-#define   GEN8_DOP_CLOCK_GATE_ENABLE           REG_BIT(0)
+#define   GEN7_DOP_CLOCK_GATE_ENABLE           REG_BIT(0)
 #define   GEN12_DOP_CLOCK_GATE_RENDER_ENABLE   REG_BIT(1)
 #define   GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE     (1 << 2)
 #define   GEN8_DOP_CLOCK_GATE_GUC_ENABLE       (1 << 4)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2e2aaea..485c5cc 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1689,7 +1689,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
        wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
 
        /* Wa_14015795083 */
-       wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+       wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
 
        /* Wa_18018781329 */
        wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
@@ -1708,7 +1708,7 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
        pvc_init_mcr(gt, wal);
 
        /* Wa_14015795083 */
-       wa_mcr_write_clr(wal, GEN8_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+       wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
 
        /* Wa_18018781329 */
        wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 3d2249b..6913342 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -39,9 +39,8 @@ static void guc_prepare_xfer(struct intel_gt *gt)
 
        if (GRAPHICS_VER(uncore->i915) == 9) {
                /* DOP Clock Gating Enable for GuC clocks */
-               intel_gt_mcr_multicast_write(gt, GEN8_MISCCPCTL,
-                                            GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
-                                            intel_gt_mcr_read_any(gt, GEN8_MISCCPCTL));
+               intel_uncore_rmw(uncore, GEN7_MISCCPCTL, 0,
+                                GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
 
                /* allows for 5us (in 10ns units) before GT can go to RC6 */
                intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 73c88b1..ac61df4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4299,8 +4299,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
        u32 val;
 
        /* WaTempDisableDOPClkGating:bdw */
-       misccpctl = intel_gt_mcr_multicast_rmw(to_gt(dev_priv), GEN8_MISCCPCTL,
-                                              GEN8_DOP_CLOCK_GATE_ENABLE, 0);
+       misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
+                                    GEN7_DOP_CLOCK_GATE_ENABLE, 0);
 
        val = intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
        val &= ~L3_PRIO_CREDITS_MASK;
@@ -4314,7 +4314,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
         */
        intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
        udelay(1);
-       intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_MISCCPCTL, misccpctl);
+       intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
 }
 
 static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -4465,8 +4465,8 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
        gen9_init_clock_gating(dev_priv);
 
        /* WaDisableDopClockGating:skl */
-       intel_gt_mcr_multicast_rmw(to_gt(dev_priv), GEN8_MISCCPCTL,
-                                  GEN8_DOP_CLOCK_GATE_ENABLE, 0);
+       intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
+                        GEN7_DOP_CLOCK_GATE_ENABLE, 0);
 
        /* WAC6entrylatency:skl */
        intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);