drivers/perf: hisi: update the sccl_id/ccl_id for certain HiSilicon platform

For some HiSilicon platform, the originally designed SCCL_ID and CCL_ID
are not satisfied with much rich topology when the MT is set, so we
extend the SCCL_ID to MPIDR[aff3] and CCL_ID to MPIDR[aff2]. Let's
update this for HiSilicon uncore PMU driver.

Cc: John Garry <john.garry@huawei.com>
Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c
index 79f76f8..96183e3 100644 (file)
--- a/drivers/perf/hisilicon/hisi_uncore_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -15,6 +15,7 @@
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 
+#include <asm/cputype.h>
 #include <asm/local64.h>
 
 #include "hisi_uncore_pmu.h"
@@ -338,8 +339,10 @@ void hisi_uncore_pmu_disable(struct pmu *pmu)
 
 /*
  * Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
- * If multi-threading is supported, CCL_ID is the low 3-bits in MPIDR[Aff2]
- * and SCCL_ID is the upper 5-bits of Aff2 field; if not, SCCL_ID
+ * If multi-threading is supported, On Huawei Kunpeng 920 SoC whose cpu
+ * core is tsv110, CCL_ID is the low 3-bits in MPIDR[Aff2] and SCCL_ID
+ * is the upper 5-bits of Aff2 field; while for other cpu types, SCCL_ID
+ * is in MPIDR[Aff3] and CCL_ID is in MPIDR[Aff2], if not, SCCL_ID
  * is in MPIDR[Aff2] and CCL_ID is in MPIDR[Aff1].
  */
 static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
@@ -347,12 +350,19 @@ static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
        u64 mpidr = read_cpuid_mpidr();
 
        if (mpidr & MPIDR_MT_BITMASK) {
-               int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
-
-               if (sccl_id)
-                       *sccl_id = aff2 >> 3;
-               if (ccl_id)
-                       *ccl_id = aff2 & 0x7;
+               if (read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
+                       int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+
+                       if (sccl_id)
+                               *sccl_id = aff2 >> 3;
+                       if (ccl_id)
+                               *ccl_id = aff2 & 0x7;
+               } else {
+                       if (sccl_id)
+                               *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
+                       if (ccl_id)
+                               *ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
+               }
        } else {
                if (sccl_id)
                        *sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);