drm/i915/cml: Separate U series pci id from origianl list.

U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Cooper Chiou <cooper.chiou@intel.com>
Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191210150415.10705-2-shawn.c.lee@intel.com

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index bba6b50..877560b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -897,6 +897,8 @@ static const struct pci_device_id pciidlist[] = {
        INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
        INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
        INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
+       INTEL_CML_U_GT1_IDS(&intel_coffeelake_gt1_info),
+       INTEL_CML_U_GT2_IDS(&intel_coffeelake_gt2_info),
        INTEL_CNL_IDS(&intel_cannonlake_info),
        INTEL_ICL_11_IDS(&intel_icelake_11_info),
        INTEL_EHL_IDS(&intel_elkhartlake_info),

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 2cde0ba..1acb5db 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -829,6 +829,8 @@ static const u16 subplatform_ult_ids[] = {
        INTEL_WHL_U_GT1_IDS(0),
        INTEL_WHL_U_GT2_IDS(0),
        INTEL_WHL_U_GT3_IDS(0),
+       INTEL_CML_U_GT1_IDS(0),
+       INTEL_CML_U_GT2_IDS(0),
 };
 
 static const u16 subplatform_ulx_ids[] = {

diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 92873c3..1d2c122 100644 (file)
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -446,19 +446,18 @@
 
 /* CML GT1 */
 #define INTEL_CML_GT1_IDS(info)        \
-       INTEL_VGA_DEVICE(0x9B21, info), \
-       INTEL_VGA_DEVICE(0x9BAA, info), \
-       INTEL_VGA_DEVICE(0x9BAC, info), \
        INTEL_VGA_DEVICE(0x9BA5, info), \
        INTEL_VGA_DEVICE(0x9BA8, info), \
        INTEL_VGA_DEVICE(0x9BA4, info), \
        INTEL_VGA_DEVICE(0x9BA2, info)
 
+#define INTEL_CML_U_GT1_IDS(info) \
+       INTEL_VGA_DEVICE(0x9B21, info), \
+       INTEL_VGA_DEVICE(0x9BAA, info), \
+       INTEL_VGA_DEVICE(0x9BAC, info)
+
 /* CML GT2 */
 #define INTEL_CML_GT2_IDS(info)        \
-       INTEL_VGA_DEVICE(0x9B41, info), \
-       INTEL_VGA_DEVICE(0x9BCA, info), \
-       INTEL_VGA_DEVICE(0x9BCC, info), \
        INTEL_VGA_DEVICE(0x9BC5, info), \
        INTEL_VGA_DEVICE(0x9BC8, info), \
        INTEL_VGA_DEVICE(0x9BC4, info), \
@@ -467,6 +466,11 @@
        INTEL_VGA_DEVICE(0x9BE6, info), \
        INTEL_VGA_DEVICE(0x9BF6, info)
 
+#define INTEL_CML_U_GT2_IDS(info) \
+       INTEL_VGA_DEVICE(0x9B41, info), \
+       INTEL_VGA_DEVICE(0x9BCA, info), \
+       INTEL_VGA_DEVICE(0x9BCC, info)
+
 #define INTEL_KBL_IDS(info) \
        INTEL_KBL_GT1_IDS(info), \
        INTEL_KBL_GT2_IDS(info), \
@@ -532,7 +536,9 @@
        INTEL_WHL_U_GT3_IDS(info), \
        INTEL_AML_CFL_GT2_IDS(info), \
        INTEL_CML_GT1_IDS(info), \
-       INTEL_CML_GT2_IDS(info)
+       INTEL_CML_GT2_IDS(info), \
+       INTEL_CML_U_GT1_IDS(info), \
+       INTEL_CML_U_GT2_IDS(info)
 
 /* CNL */
 #define INTEL_CNL_PORT_F_IDS(info) \