[AMDGPU][llvm-mc] Square-braced-syntax for registers - make ":expr2" optional.

Register numbers may be specified as assembly-time expressions.
This feature can be useful in macros and alike. However, expressions
are supported within sqare braces only.

Sqare braces were initially intended to support specifying of multiple
(pairs/quads...) registers. Syntax like v[8:8] which specifies single register
is also supported. That allows expressions but looks a bit unnatural.

This change supports syntax REG[EXPR].
Tests added.

Differential Revision: http://reviews.llvm.org/D20588

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270990 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 105074b..8883d25 100644 (file)
--- a/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -762,7 +762,7 @@ bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg,
         Parser.Lex();
         RegWidth = 1;
       } else {
-        // Range of registers: v[XX:YY].
+        // Range of registers: v[XX:YY]. ":YY" is optional.
         Parser.Lex();
         int64_t RegLo, RegHi;
         if (getLexer().isNot(AsmToken::LBrac)) { return false; }
@@ -770,14 +770,18 @@ bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg,
 
         if (getParser().parseAbsoluteExpression(RegLo)) { return false; }
 
-        if (getLexer().isNot(AsmToken::Colon)) { return false; }
+        const bool isRBrace = getLexer().is(AsmToken::RBrac);
+        if (!isRBrace && getLexer().isNot(AsmToken::Colon)) { return false; }
         Parser.Lex();
 
-        if (getParser().parseAbsoluteExpression(RegHi)) { return false; }
-
-        if (getLexer().isNot(AsmToken::RBrac)) { return false; }
-        Parser.Lex();
+        if (isRBrace) {
+          RegHi = RegLo;
+        } else {
+          if (getParser().parseAbsoluteExpression(RegHi)) { return false; }
 
+          if (getLexer().isNot(AsmToken::RBrac)) { return false; }
+          Parser.Lex();
+        }
         RegNum = (unsigned) RegLo;
         RegWidth = (RegHi - RegLo) + 1;
       }

diff --git a/test/MC/AMDGPU/reg-syntax-extra.s b/test/MC/AMDGPU/reg-syntax-extra.s
index 4f5b47e..52892a4 100644 (file)
--- a/test/MC/AMDGPU/reg-syntax-extra.s
+++ b/test/MC/AMDGPU/reg-syntax-extra.s
@@ -81,3 +81,32 @@ s_buffer_load_dword ttmp1, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4
 s_buffer_load_dwordx4 [ttmp8,ttmp9,ttmp10,ttmp11], [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4
 // SICI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
 // VI:   s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 [ttmp[8],ttmp[8+1],ttmp[5*2],ttmp[(3+2)*2+1]], ttmp[45/11:(33+45)/11], ttmp4
+// SICI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
+// VI:   s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 ttmp[7+1:(3+2)*2+1], [ttmp[45/11],ttmp[5],ttmp6,ttmp[(33+45)/11]], ttmp4
+// SICI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
+// VI:   s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
+
+flat_load_dword v[8:8], v[2:3]
+// VI:   flat_load_dword v8, v[2:3]      ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dword v[63/8+1:65/8], v[2:3]
+// VI:   flat_load_dword v8, v[2:3]      ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dword v8, v[2*2-2:(3+7)/3]
+// VI:   flat_load_dword v8, v[2:3]      ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dword v[63/8+1], v[2:3]
+// VI:   flat_load_dword v8, v[2:3]      ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dwordx4 v[8:11], v[2*2-2:(3*3-6)]
+// VI:   flat_load_dwordx4 v[8:11], v[2:3] ; encoding: [0x00,0x00,0x5c,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dwordx4 v[8/2+4:11/2+6], v[2:3]
+// VI:   flat_load_dwordx4 v[8:11], v[2:3] ; encoding: [0x00,0x00,0x5c,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dwordx4   [v[8/2+4],v9,v[10],v[11/2+6]], v[2:3]
+// VI:   flat_load_dwordx4 v[8:11], v[2:3] ; encoding: [0x00,0x00,0x5c,0xdc,0x02,0x00,0x00,0x08]