This is marginally helpful for removing redundant extensions, and the
code is easier to read, so it seems like an all-around win. In the new
test i8-phi-ext.ll, we used to emit an AssertSext i8; now we emit an
AssertZext i2, which allows the extension of the return value to be
eliminated.
Differential Revision: https://reviews.llvm.org/D49004
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336868
91177308-0d34-0410-b5e6-
96231b3b80d8
// FIXME: We capture more information than the dag can represent. For
// now, just use the tightest assertzext/assertsext possible.
- bool isSExt = true;
+ bool isSExt;
EVT FromVT(MVT::Other);
- if (NumSignBits == RegSize) {
- isSExt = true; // ASSERT SEXT 1
- FromVT = MVT::i1;
- } else if (NumZeroBits >= RegSize - 1) {
- isSExt = false; // ASSERT ZEXT 1
- FromVT = MVT::i1;
- } else if (NumSignBits > RegSize - 8) {
- isSExt = true; // ASSERT SEXT 8
- FromVT = MVT::i8;
- } else if (NumZeroBits >= RegSize - 8) {
- isSExt = false; // ASSERT ZEXT 8
- FromVT = MVT::i8;
- } else if (NumSignBits > RegSize - 16) {
- isSExt = true; // ASSERT SEXT 16
- FromVT = MVT::i16;
- } else if (NumZeroBits >= RegSize - 16) {
- isSExt = false; // ASSERT ZEXT 16
- FromVT = MVT::i16;
- } else if (NumSignBits > RegSize - 32) {
- isSExt = true; // ASSERT SEXT 32
- FromVT = MVT::i32;
- } else if (NumZeroBits >= RegSize - 32) {
- isSExt = false; // ASSERT ZEXT 32
- FromVT = MVT::i32;
+ if (NumZeroBits) {
+ FromVT = EVT::getIntegerVT(*DAG.getContext(), RegSize - NumZeroBits);
+ isSExt = false;
+ } else if (NumSignBits > 1) {
+ FromVT =
+ EVT::getIntegerVT(*DAG.getContext(), RegSize - NumSignBits + 1);
+ isSExt = true;
} else {
continue;
}
SDValue Op = N.getOperand(0);
if (Op.getOpcode() != ISD::AssertSext)
return false;
- MVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT().getSimpleVT();
+ EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
unsigned ThisBW = ty(N).getSizeInBits();
unsigned OrigBW = OrigTy.getSizeInBits();
// The type that was sign-extended to get the AssertSext must be
; GCN: s_and_saveexec_b64
; CI: v_add_i32_e32 v0, vcc, 4, [[ADD]]
-; CI: buffer_load_dword v1, v0, s[0:3], s4 offen{{$}}
+; CI: buffer_load_dword v1, v1, s[0:3], s4 offen offset:4{{$}}
; GFX9: v_add_u32_e32 v0, 4, [[ADD]]
; GFX9: buffer_load_dword v1, v{{[0-9]+}}, s[0:3], s4 offen offset:4{{$}}
--- /dev/null
+; RUN: llc < %s | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv6m---eabi"
+
+; CHECK-LABEL: test_fn
+; CHECK-NOT: uxtb
+define dso_local zeroext i8 @test_fn(i32 %x, void (...)* nocapture %f) {
+entry:
+ %tobool = icmp eq i32 %x, 0
+ br i1 %tobool, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ %callee.knr.cast = bitcast void (...)* %f to void ()*
+ tail call void %callee.knr.cast() #1
+ br label %if.end
+
+if.end: ; preds = %entry, %if.then
+ %z.0 = phi i8 [ 3, %if.then ], [ 0, %entry ]
+ ret i8 %z.0
+}
; X64-NEXT: # %bb.2:
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: xorl %edx, %edx
-; X64-NEXT: idivq %rcx
+; X64-NEXT: divq %rcx
; X64-NEXT: jmp .LBB0_3
; X64-NEXT: .LBB0_1:
; X64-NEXT: xorl %eax, %eax