arm64: dts: qcom: msm8998: Configure Adreno GPU and related IOMMU

The MSM8998 SoC includes an Adreno 540.1 GPU, with a maximum frequency
of 710MHz. This GPU may or may not accept a ZAP shader, depending on
platform configuration, so adding a zap-shader node is left to the
board DT.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210901183123.1087392-5-angelogioacchino.delregno@somainline.org

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 0fafd9e..460e6b3 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -1424,6 +1424,103 @@
                        };
                };
 
+               adreno_gpu: gpu@5000000 {
+                       compatible = "qcom,adreno-540.1", "qcom,adreno";
+                       reg = <0x05000000 0x40000>;
+                       reg-names = "kgsl_3d0_reg_memory";
+
+                       clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+                               <&gpucc RBBMTIMER_CLK>,
+                               <&gcc GCC_BIMC_GFX_CLK>,
+                               <&gcc GCC_GPU_BIMC_GFX_CLK>,
+                               <&gpucc RBCPR_CLK>,
+                               <&gpucc GFX3D_CLK>;
+                       clock-names = "iface",
+                               "rbbmtimer",
+                               "mem",
+                               "mem_iface",
+                               "rbcpr",
+                               "core";
+
+                       interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+                       iommus = <&adreno_smmu 0>;
+                       operating-points-v2 = <&gpu_opp_table>;
+                       power-domains = <&rpmpd MSM8998_VDDMX>;
+                       #stream-id-cells = <16>;
+                       status = "disabled";
+
+                       gpu_opp_table: opp-table {
+                               compatible  = "operating-points-v2";
+                               opp-710000097 {
+                                       opp-hz = /bits/ 64 <710000097>;
+                                       opp-level = <RPM_SMD_LEVEL_TURBO>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+
+                               opp-670000048 {
+                                       opp-hz = /bits/ 64 <670000048>;
+                                       opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+
+                               opp-596000097 {
+                                       opp-hz = /bits/ 64 <596000097>;
+                                       opp-level = <RPM_SMD_LEVEL_NOM>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+
+                               opp-515000097 {
+                                       opp-hz = /bits/ 64 <515000097>;
+                                       opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+
+                               opp-414000000 {
+                                       opp-hz = /bits/ 64 <414000000>;
+                                       opp-level = <RPM_SMD_LEVEL_SVS>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+
+                               opp-342000000 {
+                                       opp-hz = /bits/ 64 <342000000>;
+                                       opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+
+                               opp-257000000 {
+                                       opp-hz = /bits/ 64 <257000000>;
+                                       opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                       };
+               };
+
+               adreno_smmu: iommu@5040000 {
+                       compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
+                       reg = <0x05040000 0x10000>;
+                       clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+                                <&gcc GCC_BIMC_GFX_CLK>,
+                                <&gcc GCC_GPU_BIMC_GFX_CLK>;
+                       clock-names = "iface", "mem", "mem_iface";
+
+                       #global-interrupts = <0>;
+                       #iommu-cells = <1>;
+                       interrupts =
+                               <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+                       /*
+                        * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
+                        * GPU-CX for SMMU but we need both of them up for Adreno.
+                        * Contemporarily, we also need to manage the VDDMX rpmpd
+                        * domain in the Adreno driver.
+                        * Enable GPU CX/GX GDSCs here so that we can manage the
+                        * SoC VDDMX RPM Power Domain in the Adreno driver.
+                        */
+                       power-domains = <&gpucc GPU_GX_GDSC>;
+                       status = "disabled";
+               };
+
                gpucc: clock-controller@5065000 {
                        compatible = "qcom,msm8998-gpucc";
                        #clock-cells = <1>;