The previous attempt was fine with optimisations, but was actually rather
cavalier with its types. When compiled at -O0, it produced invalid COPY
MachineInstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205422
91177308-0d34-0410-b5e6-
96231b3b80d8
return true;
}
+ case ARM64::FCVTSHpseudo: {
+ MachineOperand Src = MI.getOperand(1);
+ Src.setImplicit();
+ unsigned SrcH = TII->getRegisterInfo().getSubReg(Src.getReg(), ARM64::hsub);
+ auto MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM64::FCVTSHr))
+ .addOperand(MI.getOperand(0))
+ .addReg(SrcH, RegState::Undef)
+ .addOperand(Src);
+ transferImpOps(MI, MIB, MIB);
+ MI.eraseFromParent();
+ return true;
+ }
case ARM64::LOADgot: {
// Expand into ADRP + LDR.
unsigned DstReg = MI.getOperand(0).getReg();
break;
}
- case ISD::FP16_TO_FP32: {
- assert(Node->getOperand(0).getValueType() == MVT::i32 && "vector convert?");
- EVT VT = Node->getValueType(0);
- SDLoc DL(Node);
- SDValue FPR32Id =
- CurDAG->getTargetConstant(ARM64::FPR32RegClass.getID(), MVT::i32);
- SDNode *Res =
- CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DL, MVT::i32,
- Node->getOperand(0), FPR32Id);
- SDValue FPR16Reg =
- CurDAG->getTargetExtractSubreg(ARM64::hsub, DL, VT, SDValue(Res, 0));
- return CurDAG->getMachineNode(ARM64::FCVTSHr, DL, VT, FPR16Reg);
- }
case ISD::SRL:
case ISD::AND:
case ISD::SRA:
(f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
GPR32))>;
+def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
+ [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
//===----------------------------------------------------------------------===//
// Floating point single operand instructions.
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -O0 -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
define <2 x double> @test_vcvt_f64_f32(<2 x float> %x) nounwind readnone ssp {
; CHECK-LABEL: test_vcvt_f64_f32:
define i16 @to_half(float %in) {
; CHECK-LABEL: to_half:
; CHECK: fcvt h[[HALFVAL:[0-9]+]], s0
-; CHECK: fmov w0, s[[HALFVAL]]
-
+; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}}
%res = call i16 @llvm.convert.to.fp16(float %in)
ret i16 %res
}