Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57210 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 494ac1d..d74588e 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -3954,6 +3954,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
 
   // Canonicalize movddup shuffles.
   if (V2IsUndef && Subtarget->hasSSE2() &&
+      VT.getSizeInBits() == 128 &&
       X86::isMOVDDUPMask(PermMask.getNode()))
     return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
 

diff --git a/test/CodeGen/X86/2008-10-06-MMXISelBug.ll b/test/CodeGen/X86/2008-10-06-MMXISelBug.ll
new file mode 100644 (file)
index 0000000..bd1ad59
--- /dev/null
+++ b/test/CodeGen/X86/2008-10-06-MMXISelBug.ll
@@ -0,0 +1,12 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+mmx,+sse2
+; PR2850
+
+@tmp_V2i = common global <2 x i32> zeroinitializer             ; <<2 x i32>*> [#uses=2]
+
+define void @f0() nounwind {
+entry:
+       %0 = load <2 x i32>* @tmp_V2i, align 8          ; <<2 x i32>> [#uses=1]
+       %1 = shufflevector <2 x i32> %0, <2 x i32> undef, <2 x i32> zeroinitializer             ; <<2 x i32>> [#uses=1]
+       store <2 x i32> %1, <2 x i32>* @tmp_V2i, align 8
+       ret void
+}