r_nw, oam_bus_ce_n, oam_addr, oam_data,
plt_bus_ce_n, plt_addr, plt_data);
--- render_ad_buf : tri_state_buffer generic map (dsize)
--- port map ('0', render_vram_ad, vram_ad);
--- render_d_buf : tri_state_buffer generic map (6)
--- port map ('0', render_vram_a, vram_a);
-
vga_inst : vga_ctl port map (clk, vga_clk, rst_n,
pos_x, pos_y, nes_r, nes_g, nes_b,
h_sync_n, v_sync_n, r, g, b);
ppu_addr_cnt_ce_n <= '0';
ppu_addr_we_n <= '0';
if (ppu_addr_cnt(0) = '0') then
+ --if address is 3fxx, set palette table.
ppu_addr_in <= cpu_d(5 downto 0) & ppu_addr(7 downto 0);
- ale <= '1';
else
ppu_addr_in <= ppu_addr(13 downto 8) & cpu_d;
- vram_ad <= ppu_addr(7 downto 0);
- vram_a <= ppu_addr(13 downto 8);
- ale <= '0';
+ if (ppu_addr(13 downto 8) = "111111") then
+ plt_addr <= cpu_d(4 downto 0);
+ ale <= '0';
+ else
+ vram_ad <= cpu_d;
+ vram_a <= ppu_addr(13 downto 8);
+ ale <= '1';
+ end if;
end if;
else
ppu_addr_cnt_ce_n <= '1';
ppu_addr_we_n <= '1';
- ale <= '1';
+ ale <= '0';
end if;
if(cpu_addr = PPUDATA) then
ppu_data_we_n <= '0';
rd_n <= not r_nw;
wr_n <= r_nw;
+ if (ppu_addr(13 downto 8) = "111111") then
+ --case palette tbl.
+ plt_bus_ce_n <= '0';
+ plt_data <= cpu_d(5 downto 0);
+ else
+ plt_bus_ce_n <= '1';
+ if (r_nw = '0') then
+ vram_ad <= cpu_d;
+ end if;
+ end if;
else
+ plt_bus_ce_n <= '1';
ppu_data_we_n <= '1';
rd_n <= '1';
wr_n <= '1';
ppu_addr_cnt_ce_n <= '1';
ppu_data_we_n <= '1';
+ plt_bus_ce_n <= '1';
+
ale <= 'Z';
rd_n <= 'Z';
wr_n <= 'Z';
vram_ad <= (others => 'Z');
vram_a <= (others => 'Z');
end if; --if (ce_n = '0') then
- else
end if;--if (clk'event and clk = '1') then
end process;
-----test init value set.
--- p_palette_init : process
--- variable i : integer := 0;
---use ieee.std_logic_arith.all;
---constant ppu_clk_time : time := 186 ns;
--- begin
--- wait for 7 us;
---
--- --fill palette teble.
--- plt_bus_ce_n <= '0';
--- plt_r_nw <= '0';
--- for i in 0 to 32 loop
--- plt_addr <= conv_std_logic_vector(i, 5);
--- plt_data <= conv_std_logic_vector((i - 1) * 4 + 17, 6);
--- wait for ppu_clk_time;
--- end loop;
--- plt_bus_ce_n <= '1';
---
--- ---TODO: for the time being...
--- plt_bus_ce_n <= 'Z';
--- plt_r_nw <= 'Z';
--- plt_addr <= (others => 'Z');
--- plt_data <= (others => 'Z');
---
--- wait;
--- end process;
-
end rtl;
);
end component;
- component test_module_init_data
- port ( clk : in std_logic;
- v_rd_n : out std_logic;
- v_wr_n : out std_logic;
- v_ale : out std_logic;
- v_ad : out std_logic_vector (7 downto 0);
- v_a : out std_logic_vector (13 downto 8);
- cpu_addr : out std_logic_vector (2 downto 0);
- cpu_d : out std_logic_vector (7 downto 0)
- );
- end component;
-
component vga_device
port ( vga_clk : in std_logic;
rst_n : in std_logic;
vblank_n, rd_n, wr_n, ale, vram_ad, vram_a,
vga_clk, h_sync_n, v_sync_n, r, g, b);
--- -----fill test data during the reset.....
--- init_data : test_module_init_data
--- port map (clk, rd_n, wr_n, ale, vram_ad, vram_a,
--- cpu_addr, cpu_d);
-
ppu_addr_decoder : v_address_decoder generic map (size14, size8)
port map (clk, rd_n, wr_n, ale, vram_ad, vram_a);
wait for vga_clk_time / 2;
end process;
+ --test data set.
test_init_p : process
variable i : integer := 0;
- constant loopcnt : integer := 15;
+ constant loopcnt : integer := 40;
begin
wait for test_init_time + test_reset_time + ppu_clk_time / 2;
ce_n <= '0';
wait for ppu_clk_time;
--attr tbl set.
--- cpu_addr <= "110";
--- cpu_d <= conv_std_logic_vector(16#23c0# + i, 16)(15 downto 8);
--- wait for ppu_clk_time;
--- cpu_d <= conv_std_logic_vector(16#23c0# + i, 16)(7 downto 0);
--- wait for ppu_clk_time;
--- cpu_addr <= "111";
--- cpu_d <= conv_std_logic_vector(16#5a# + 3 * i, 8);
--- wait for ppu_clk_time;
+ cpu_addr <= "110";
+ cpu_d <= conv_std_logic_vector(16#23c0# + i, 16)(15 downto 8);
+ wait for ppu_clk_time;
+ cpu_d <= conv_std_logic_vector(16#23c0# + i, 16)(7 downto 0);
+ wait for ppu_clk_time;
+ cpu_addr <= "111";
+ cpu_d <= conv_std_logic_vector(16#5a# + 3 * i, 8);
+ wait for ppu_clk_time;
+
+ --palette tbl set.
+ cpu_addr <= "110";
+ cpu_d <= conv_std_logic_vector(16#3f00# + i, 16)(15 downto 8);
+ wait for ppu_clk_time;
+ cpu_d <= conv_std_logic_vector(16#3f00# + i, 16)(7 downto 0);
+ wait for ppu_clk_time;
+ cpu_addr <= "111";
+ cpu_d <= conv_std_logic_vector((i - 1 ) * 4 + 17, 8);
+ wait for ppu_clk_time;
end loop;
--enable show bg.
end stimulus ;
-
-
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
--- initialize with dummy data
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
-------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-
-entity test_module_init_data is
- port ( clk : in std_logic;
- v_rd_n : out std_logic;
- v_wr_n : out std_logic;
- v_ale : out std_logic;
- v_ad : out std_logic_vector (7 downto 0);
- v_a : out std_logic_vector (13 downto 8);
- cpu_addr : out std_logic_vector (2 downto 0);
- cpu_d : out std_logic_vector (7 downto 0)
- );
-end test_module_init_data;
-
-architecture stimulus of test_module_init_data is
-
- constant ppu_clk : time := 186 ns;
- constant size8 : integer := 8;
- constant size16 : integer := 16;
- constant size14 : integer := 14;
-
-constant test_init_time : time := 7 us;
-constant test_reset_time : time := 20 us;
-
- signal v_addr : std_logic_vector (size14 - 1 downto 0);
-
-begin
-
- v_ad <= v_addr(size8 - 1 downto 0);
- v_a <= v_addr(size14 - 1 downto size8);
-
- -----test for vram/chr-rom
- p_vram_init : process
- variable i : integer := 0;
- variable tmp : std_logic_vector (size8 - 1 downto 0);
- constant loopcnt : integer := 15;
- begin
-
- ---dummy power up wait (same amount of time as testbench)
- wait for test_init_time;
-
- --copy from chr rom to name tbl.
- for i in 0 to loopcnt loop
- --write name tbl #0
- v_ale <= '1';
- v_rd_n <= '1';
- v_wr_n <= '1';
- v_addr <= conv_std_logic_vector(16#2000# + i, size14);
- wait for ppu_clk;
- v_addr(7 downto 0) <= (others => 'Z');
- v_ale <= '0';
- v_rd_n <= '1';
- v_wr_n <= '0';
- ---bg start from 0.
- v_addr(7 downto 0) <= conv_std_logic_vector(i + 32, size8);
- wait for ppu_clk;
-
- --write attr tbl #0
- v_ale <= '1';
- v_rd_n <= '1';
- v_wr_n <= '1';
- v_addr <= conv_std_logic_vector(16#23c0# + i, size14);
- wait for ppu_clk;
- v_addr(7 downto 0) <= (others => 'Z');
- v_ale <= '0';
- v_rd_n <= '1';
- v_wr_n <= '0';
- v_addr(7 downto 0) <= conv_std_logic_vector(16#a0# + i, size8);
- wait for ppu_clk;
- end loop;
-
- v_ale <= 'Z';
- v_rd_n <= 'Z';
- v_wr_n <= 'Z';
- v_addr <= (others => 'Z');
-
- wait;
- end process;
-
--- p_palette_init : process
--- variable i : integer := 0;
--- begin
--- wait for 7 us;
---
--- --fill palette teble.
--- plt_bus_ce_n <= '0';
--- plt_r_nw <= '0';
--- for i in 0 to 32 loop
--- plt_addr <= conv_std_logic_vector(i, 5);
--- plt_data <= conv_std_logic_vector((i - 1) * 4 + 17, 6);
--- wait for ppu_clk;
--- end loop;
--- plt_bus_ce_n <= '1';
--- plt_data <= (others => 'Z');
---
--- wait;
--- end process;
-
-end stimulus ;
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