[ opcodes/ChangeLog ]

2002-12-18  Chris Demetriou  <cgd@broadcom.com>

	* mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
	"dror" entries, and reorder the remaining "dror" and "ror" entries.

[ gas/ChangeLog ]
2002-12-18  Chris Demetriou  <cgd@broadcom.com>

	* config/tc-mips.c (macro): In M_DROL, M_DROR, M_ROL, and M_ROR,
	use hardware rotate ops as appropriate.  In M_DROL_I, M_DROR_I,
	M_ROL_I, and M_ROR_I, simplify code, clean up warnings, and
	arrange not to issue warnings about use of AT when AT is not
	actually used.

[ gas/testsuite/ChangeLog ]
2002-12-18  Chris Demetriou  <cgd@broadcom.com>

	* gas/mips/rol.s: Add ".set noat" and some new instructions to test.
	* gas/mips/rol64.s: Likewise.
	* gas/mips/rol.l: New file.
	* gas/mips/rol.d: Adjust to use rol.l and for rol.s changes.
	* gas/mips/rol64.l: New file.
	* gas/mips/rol64.d: Adjust to use rol64.l and for rol64.s changes.
	* gas/mips/rol-hw.d: New file.
	* gas/mips/rol-hw.l: New file.
	* gas/mips/rol64-hw.d: New file.
	* gas/mips/rol64-hw.l: New file.
	* gas/mips/mips.exp: Run rol-hw and rol64-hw tests.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 92715e3..9b6cc95 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2002-12-18  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two
+       "dror" entries, and reorder the remaining "dror" and "ror" entries.
+
 2002-12-16  DJ Delorie  <dj@delorie.com>
 
        * xstormy16-asm.c (parse_immediate16): Add prototype.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 7dae28a..61a2ebd 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -550,13 +550,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dret",    "",                0x7000003e, 0xffffffff, 0,                      N5      },
 {"drol",    "d,v,t",   0,    (int) M_DROL,     INSN_MACRO,             I3      },
 {"drol",    "d,v,I",   0,    (int) M_DROL_I,   INSN_MACRO,             I3      },
-{"drorv",   "d,t,s",   0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         N5      },
-{"dror32",  "d,w,<",   0x0020003e, 0xffe0003f, WR_d|RD_t,              N5      },
-{"dror",    "d,w,s",   0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         N5      }, /* drorv */
-{"dror",    "d,w,>",   0x0020003e, 0xffe0003f, WR_d|RD_t,              N5      },
-{"dror",    "d,w,<",   0x0020003a, 0xffe0003f, WR_d|RD_t,              N5      },
 {"dror",    "d,v,t",   0,    (int) M_DROR,     INSN_MACRO,             I3      },
 {"dror",    "d,v,I",   0,    (int) M_DROR_I,   INSN_MACRO,             I3      },
+{"dror",    "d,w,<",   0x0020003a, 0xffe0003f, WR_d|RD_t,              N5      },
+{"drorv",   "d,t,s",   0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         N5      },
+{"dror32",  "d,w,<",   0x0020003e, 0xffe0003f, WR_d|RD_t,              N5      },
 {"dsllv",   "d,t,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      },
 {"dsll32",  "d,w,<",   0x0000003c, 0xffe0003f, WR_d|RD_t,              I3      },
 {"dsll",    "d,w,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         I3      }, /* dsllv */
@@ -901,11 +899,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"rneu.qh", "X,Q",     0x78200022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX      },
 {"rol",     "d,v,t",   0,    (int) M_ROL,      INSN_MACRO,             I1      },
 {"rol",     "d,v,I",   0,    (int) M_ROL_I,    INSN_MACRO,             I1      },
-{"rorv",    "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         N5      },
-{"ror",     "d,w,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         N5      }, /* rorv */
-{"ror",            "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              N5      },
 {"ror",     "d,v,t",   0,    (int) M_ROR,      INSN_MACRO,             I1      },
 {"ror",     "d,v,I",   0,    (int) M_ROR_I,    INSN_MACRO,             I1      },
+{"ror",            "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              N5      },
+{"rorv",    "d,t,s",   0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         N5      },
 {"round.l.d", "D,S",   0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         I3      },
 {"round.l.s", "D,S",   0x46000008, 0xffff003f, WR_D|RD_S|FP_S,         I3      },
 {"round.w.d", "D,S",   0x4620000c, 0xffff003f, WR_D|RD_S|FP_D,         I2      },