New sim testsuite for Fujitsu FRV. Contributed by Red Hat.

diff --git a/sim/testsuite/sim/frv/fr500/allinsn.exp b/sim/testsuite/sim/frv/fr500/allinsn.exp
new file mode 100644 (file)
index 0000000..a5953fb
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/allinsn.exp
@@ -0,0 +1,19 @@
+# FRV simulator testsuite.
+
+if [istarget frv*-*] {
+    # load support procs (none yet)
+    # load_lib cgen.exp
+    # all machines
+    set all_machs "frv fr500"
+    set cpu_option -mcpu
+
+    # The .cgs suffix is for "cgen .s".
+    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.cgs]] {
+       # If we're only testing specific files and this isn't one of them,
+       # skip it.
+       if ![runtest_file_p $runtests $src] {
+           continue
+       }
+       run_sim_test $src $all_machs
+    }
+}

diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs
new file mode 100644 (file)
index 0000000..42c4ee3
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/cmqaddhss.cgs
@@ -0,0 +1,444 @@
+# frv testcase for cmqaddhss $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global cmqaddhss
+cmqaddhss:
+       set_spr_immed   0x1b1b,cccr
+
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhss       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0xbeef,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhss       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0xbeef,0xdead,fr14
+       test_fr_limmed  0x2345,0x6789,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqaddhss       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0x1233,0x5677,fr14
+       test_fr_limmed  0x7fff,0x7fff,fr15
+       test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0xffff,0xfffe,fr12
+       set_fr_iimmed   0xfffe,0xfffe,fr13
+       cmqaddhss       fr10,fr12,fr14,cc4,1
+       test_fr_limmed  0x8000,0x8000,fr14
+       test_fr_limmed  0x8000,0x8000,fr15
+       test_spr_bits   0x3c,2,0x7,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x7fff,0x0000,fr12
+       set_fr_iimmed   0x0000,0x8000,fr13
+       cmqaddhss.p     fr10,fr10,fr14,cc4,1
+       cmqaddhss       fr12,fr12,fr16,cc4,1
+       test_fr_limmed  0x0002,0x0002,fr14
+       test_fr_limmed  0xfffe,0xfffe,fr15
+       test_fr_limmed  0x7fff,0x0000,fr16
+       test_fr_limmed  0x0000,0x8000,fr17
+       test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie not set
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0x9,msr1         ; msr1.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhss       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0xbeef,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhss       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0xbeef,0xdead,fr14
+       test_fr_limmed  0x2345,0x6789,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqaddhss       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0x1233,0x5677,fr14
+       test_fr_limmed  0x7fff,0x7fff,fr15
+       test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0xffff,0xfffe,fr12
+       set_fr_iimmed   0xfffe,0xfffe,fr13
+       cmqaddhss       fr10,fr12,fr14,cc5,0
+       test_fr_limmed  0x8000,0x8000,fr14
+       test_fr_limmed  0x8000,0x8000,fr15
+       test_spr_bits   0x3c,2,0x7,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x7fff,0x0000,fr12
+       set_fr_iimmed   0x0000,0x8000,fr13
+       cmqaddhss.p     fr10,fr10,fr14,cc5,0
+       cmqaddhss       fr12,fr12,fr16,cc5,0
+       test_fr_limmed  0x0002,0x0002,fr14
+       test_fr_limmed  0xfffe,0xfffe,fr15
+       test_fr_limmed  0x7fff,0x0000,fr16
+       test_fr_limmed  0x0000,0x8000,fr17
+       test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie not set
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0x9,msr1         ; msr1.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhss       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhss       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqaddhss       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0xffff,0xfffe,fr12
+       set_fr_iimmed   0xfffe,0xfffe,fr13
+       cmqaddhss       fr10,fr12,fr14,cc4,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x7fff,0x0000,fr12
+       set_fr_iimmed   0x0000,0x8000,fr13
+       cmqaddhss.p     fr10,fr10,fr14,cc4,0
+       cmqaddhss       fr12,fr12,fr16,cc4,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhss       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhss       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqaddhss       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0xffff,0xfffe,fr12
+       set_fr_iimmed   0xfffe,0xfffe,fr13
+       cmqaddhss       fr10,fr12,fr14,cc5,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x7fff,0x0000,fr12
+       set_fr_iimmed   0x0000,0x8000,fr13
+       cmqaddhss.p     fr10,fr10,fr14,cc5,1
+       cmqaddhss       fr12,fr12,fr16,cc5,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhss       fr10,fr12,fr14,cc2,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhss       fr10,fr12,fr14,cc2,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqaddhss       fr10,fr12,fr14,cc2,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0xffff,0xfffe,fr12
+       set_fr_iimmed   0xfffe,0xfffe,fr13
+       cmqaddhss       fr10,fr12,fr14,cc6,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x7fff,0x0000,fr12
+       set_fr_iimmed   0x0000,0x8000,fr13
+       cmqaddhss.p     fr10,fr10,fr14,cc6,1
+       cmqaddhss       fr12,fr12,fr16,cc6,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+;
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhss       fr10,fr12,fr14,cc3,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhss       fr10,fr12,fr14,cc3,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqaddhss       fr10,fr12,fr14,cc3,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0xffff,0xfffe,fr12
+       set_fr_iimmed   0xfffe,0xfffe,fr13
+       cmqaddhss       fr10,fr12,fr14,cc7,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x7fff,0x0000,fr12
+       set_fr_iimmed   0x0000,0x8000,fr13
+       cmqaddhss.p     fr10,fr10,fr14,cc7,1
+       cmqaddhss       fr12,fr12,fr16,cc7,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs b/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs
new file mode 100644 (file)
index 0000000..325f532
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/cmqaddhus.cgs
@@ -0,0 +1,360 @@
+# frv testcase for cmqaddhus $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global cmqaddhus
+cmqaddhus:
+       set_spr_immed   0x1b1b,cccr
+
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhus       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0xbeef,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhus       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0xbeef,0xdead,fr14
+       test_fr_limmed  0x2345,0x6789,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x7ffe,0x7ffe,fr10
+       set_fr_iimmed   0xfffe,0xfffe,fr11
+       set_fr_iimmed   0x0002,0x0001,fr12
+       set_fr_iimmed   0x0001,0x0002,fr13
+       cmqaddhus       fr10,fr12,fr14,cc4,1
+       test_fr_limmed  0x8000,0x7fff,fr14
+       test_fr_limmed  0xffff,0xffff,fr15
+       test_spr_bits   0x3c,2,1,msr0           ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0002,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0xfffe,0xfffe,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqaddhus.p     fr10,fr10,fr14,cc4,1
+       cmqaddhus       fr12,fr12,fr16,cc4,1
+       test_fr_limmed  0x0004,0x0002,fr14
+       test_fr_limmed  0x0002,0x0002,fr15
+       test_fr_limmed  0xffff,0xffff,fr16
+       test_fr_limmed  0xffff,0xffff,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0xf,msr1         ; msr1.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhus       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0xbeef,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhus       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0xbeef,0xdead,fr14
+       test_fr_limmed  0x2345,0x6789,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x7ffe,0x7ffe,fr10
+       set_fr_iimmed   0xfffe,0xfffe,fr11
+       set_fr_iimmed   0x0002,0x0001,fr12
+       set_fr_iimmed   0x0001,0x0002,fr13
+       cmqaddhus       fr10,fr12,fr14,cc5,0
+       test_fr_limmed  0x8000,0x7fff,fr14
+       test_fr_limmed  0xffff,0xffff,fr15
+       test_spr_bits   0x3c,2,1,msr0           ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0002,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0xfffe,0xfffe,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqaddhus.p     fr10,fr10,fr14,cc5,0
+       cmqaddhus       fr12,fr12,fr16,cc5,0
+       test_fr_limmed  0x0004,0x0002,fr14
+       test_fr_limmed  0x0002,0x0002,fr15
+       test_fr_limmed  0xffff,0xffff,fr16
+       test_fr_limmed  0xffff,0xffff,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0xf,msr1         ; msr1.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhus       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhus       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x7ffe,0x7ffe,fr10
+       set_fr_iimmed   0xfffe,0xfffe,fr11
+       set_fr_iimmed   0x0002,0x0001,fr12
+       set_fr_iimmed   0x0001,0x0002,fr13
+       cmqaddhus       fr10,fr12,fr14,cc4,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0002,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0xfffe,0xfffe,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqaddhus.p     fr10,fr10,fr14,cc4,0
+       cmqaddhus       fr12,fr12,fr16,cc4,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhus       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhus       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x7ffe,0x7ffe,fr10
+       set_fr_iimmed   0xfffe,0xfffe,fr11
+       set_fr_iimmed   0x0002,0x0001,fr12
+       set_fr_iimmed   0x0001,0x0002,fr13
+       cmqaddhus       fr10,fr12,fr14,cc5,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0002,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0xfffe,0xfffe,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqaddhus.p     fr10,fr10,fr14,cc5,1
+       cmqaddhus       fr12,fr12,fr16,cc5,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhus       fr10,fr12,fr14,cc2,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhus       fr10,fr12,fr14,cc2,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x7ffe,0x7ffe,fr10
+       set_fr_iimmed   0xfffe,0xfffe,fr11
+       set_fr_iimmed   0x0002,0x0001,fr12
+       set_fr_iimmed   0x0001,0x0002,fr13
+       cmqaddhus       fr10,fr12,fr14,cc6,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0002,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0xfffe,0xfffe,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqaddhus.p     fr10,fr10,fr14,cc6,0
+       cmqaddhus       fr12,fr12,fr16,cc6,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqaddhus       fr10,fr12,fr14,cc3,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqaddhus       fr10,fr12,fr14,cc3,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x7ffe,0x7ffe,fr10
+       set_fr_iimmed   0xfffe,0xfffe,fr11
+       set_fr_iimmed   0x0002,0x0001,fr12
+       set_fr_iimmed   0x0001,0x0002,fr13
+       cmqaddhus       fr10,fr12,fr14,cc7,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0002,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0xfffe,0xfffe,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqaddhus.p     fr10,fr10,fr14,cc7,0
+       cmqaddhus       fr12,fr12,fr16,cc7,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs
new file mode 100644 (file)
index 0000000..3cfa2ef
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/cmqsubhss.cgs
@@ -0,0 +1,448 @@
+# frv testcase for cmqsubhss $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global msubhss
+msubhss:
+       set_spr_immed   0x1b1b,cccr
+
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqsubhss       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0x4111,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqsubhss       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0x4111,0xdead,fr14
+       test_fr_limmed  0x0123,0x4567,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0xfffe,0xffff,fr13
+       cmqsubhss       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0x1235,0x5679,fr14
+       test_fr_limmed  0x7fff,0x7fff,fr15
+       test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhss       fr10,fr12,fr14,cc4,1
+       test_fr_limmed  0x8000,0x8000,fr14
+       test_fr_limmed  0x8000,0x8000,fr15
+       test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x8000,0x8000,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqsubhss.p     fr10,fr10,fr14,cc4,1
+       cmqsubhss       fr12,fr10,fr16,cc4,1
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0x0000,0x0000,fr15
+       test_fr_limmed  0x8000,0x8000,fr16
+       test_fr_limmed  0x8001,0x8001,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0xc,msr1         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqsubhss       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0x4111,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqsubhss       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0x4111,0xdead,fr14
+       test_fr_limmed  0x0123,0x4567,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0xfffe,0xffff,fr13
+       cmqsubhss       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0x1235,0x5679,fr14
+       test_fr_limmed  0x7fff,0x7fff,fr15
+       test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhss       fr10,fr12,fr14,cc5,0
+       test_fr_limmed  0x8000,0x8000,fr14
+       test_fr_limmed  0x8000,0x8000,fr15
+       test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x8000,0x8000,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqsubhss.p     fr10,fr10,fr14,cc5,0
+       cmqsubhss       fr12,fr10,fr16,cc5,0
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0x0000,0x0000,fr15
+       test_fr_limmed  0x8000,0x8000,fr16
+       test_fr_limmed  0x8001,0x8001,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0xc,msr1         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqsubhss       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqsubhss       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0xfffe,0xffff,fr13
+       cmqsubhss       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhss       fr10,fr12,fr14,cc4,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x8000,0x8000,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqsubhss.p     fr10,fr10,fr14,cc4,0
+       cmqsubhss       fr12,fr10,fr16,cc4,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqsubhss       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqsubhss       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0xfffe,0xffff,fr13
+       cmqsubhss       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhss       fr10,fr12,fr14,cc5,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x8000,0x8000,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqsubhss.p     fr10,fr10,fr14,cc5,1
+       cmqsubhss       fr12,fr10,fr16,cc5,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqsubhss       fr10,fr12,fr14,cc2,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqsubhss       fr10,fr12,fr14,cc2,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0xfffe,0xffff,fr13
+       cmqsubhss       fr10,fr12,fr14,cc2,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhss       fr10,fr12,fr14,cc6,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x8000,0x8000,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqsubhss.p     fr10,fr10,fr14,cc6,1
+       cmqsubhss       fr12,fr10,fr16,cc6,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       cmqsubhss       fr10,fr12,fr14,cc3,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       cmqsubhss       fr10,fr12,fr14,cc3,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0xfffe,0xffff,fr13
+       cmqsubhss       fr10,fr12,fr14,cc3,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhss       fr10,fr12,fr14,cc7,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x8000,0x8000,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       cmqsubhss.p     fr10,fr10,fr14,cc7,1
+       cmqsubhss       fr12,fr10,fr16,cc7,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_fr_limmed  0x4444,0x4444,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs b/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs
new file mode 100644 (file)
index 0000000..646565d
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/cmqsubhus.cgs
@@ -0,0 +1,370 @@
+# frv testcase for cmqsubhus $FRi,$FRj,$FRj,$CCi,$cond
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global cmqsubhus
+cmqsubhus:
+       set_spr_immed   0x1b1b,cccr
+
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0xbeef,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0x0000,fr13
+       cmqsubhus       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0xbeef,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0x1111,0x1111,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc0,1
+       test_fr_limmed  0x0123,0x4567,fr14
+       test_fr_limmed  0x7ffc,0x7ffd,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc4,1
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0x0000,0x0000,fr15
+       test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0002,0x0002,fr11
+       set_fr_iimmed   0x0000,0x0001,fr12
+       set_fr_iimmed   0x0002,0x0003,fr13
+       cmqsubhus.p     fr10,fr10,fr14,cc4,1
+       cmqsubhus       fr10,fr12,fr16,cc4,1
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0x0000,0x0000,fr15
+       test_fr_limmed  0x0001,0x0000,fr16
+       test_fr_limmed  0x0000,0x0000,fr17
+       test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0x1,msr1         ; msr1.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0xbeef,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0x0000,fr13
+       cmqsubhus       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0xbeef,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0x1111,0x1111,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc1,0
+       test_fr_limmed  0x0123,0x4567,fr14
+       test_fr_limmed  0x7ffc,0x7ffd,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc5,0
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0x0000,0x0000,fr15
+       test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0002,0x0002,fr11
+       set_fr_iimmed   0x0000,0x0001,fr12
+       set_fr_iimmed   0x0002,0x0003,fr13
+       cmqsubhus.p     fr10,fr10,fr14,cc5,0
+       cmqsubhus       fr10,fr12,fr16,cc5,0
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0x0000,0x0000,fr15
+       test_fr_limmed  0x0001,0x0000,fr16
+       test_fr_limmed  0x0000,0x0000,fr17
+       test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0x1,msr1         ; msr1.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0xbeef,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0x0000,fr13
+       cmqsubhus       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0x1111,0x1111,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc0,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc4,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0002,0x0002,fr11
+       set_fr_iimmed   0x0000,0x0001,fr12
+       set_fr_iimmed   0x0002,0x0003,fr13
+       cmqsubhus.p     fr10,fr10,fr14,cc4,0
+       cmqsubhus       fr10,fr12,fr16,cc4,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+       test_fr_limmed  0x4444,0x4444,fr17
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0xbeef,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0x0000,fr13
+       cmqsubhus       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0x1111,0x1111,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc1,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc5,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0002,0x0002,fr11
+       set_fr_iimmed   0x0000,0x0001,fr12
+       set_fr_iimmed   0x0002,0x0003,fr13
+       cmqsubhus.p     fr10,fr10,fr14,cc5,1
+       cmqsubhus       fr10,fr12,fr16,cc5,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+       test_fr_limmed  0x4444,0x4444,fr17
+
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0xbeef,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0x0000,fr13
+       cmqsubhus       fr10,fr12,fr14,cc2,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0x1111,0x1111,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc2,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc6,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0002,0x0002,fr11
+       set_fr_iimmed   0x0000,0x0001,fr12
+       set_fr_iimmed   0x0002,0x0003,fr13
+       cmqsubhus.p     fr10,fr10,fr14,cc6,0
+       cmqsubhus       fr10,fr12,fr16,cc6,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+       test_fr_limmed  0x4444,0x4444,fr17
+;
+       set_fr_iimmed   0x1111,0x1111,fr14
+       set_fr_iimmed   0x2222,0x2222,fr15
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0xbeef,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0x0000,fr13
+       cmqsubhus       fr10,fr12,fr14,cc3,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0x1111,0x1111,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc3,0
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       cmqsubhus       fr10,fr12,fr14,cc7,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x3333,0x3333,fr16
+       set_fr_iimmed   0x4444,0x4444,fr17
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0002,0x0002,fr11
+       set_fr_iimmed   0x0000,0x0001,fr12
+       set_fr_iimmed   0x0002,0x0003,fr13
+       cmqsubhus.p     fr10,fr10,fr14,cc7,0
+       cmqsubhus       fr10,fr12,fr16,cc7,1
+       test_fr_limmed  0x1111,0x1111,fr14
+       test_fr_limmed  0x2222,0x2222,fr15
+       test_fr_limmed  0x3333,0x3333,fr16
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   2,1,0,msr1              ; msr1.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+       test_fr_limmed  0x4444,0x4444,fr17
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/dcpl.cgs b/sim/testsuite/sim/frv/fr500/dcpl.cgs
new file mode 100644 (file)
index 0000000..30ed7ff
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/dcpl.cgs
@@ -0,0 +1,65 @@
+# FRV testcase for dcpl GRi,GRj,lock
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global dcpl
+dcpl:
+       or_spr_immed    0xc8000000,hsr0 ; caches enabled -- copy-back mode
+
+       ; preload and lock all the lines in set 0 of the data cache
+       set_gr_immed    0x70000,gr10
+       dcpl            gr10,gr0,1
+       set_mem_immed   0x11111111,gr10
+       test_mem_immed  0x11111111,gr10
+
+       inc_gr_immed    0x1000,gr10
+       set_gr_immed    1,gr11
+       dcpl            gr10,gr11,1
+       set_mem_immed   0x22222222,gr10
+       test_mem_immed  0x22222222,gr10
+
+       inc_gr_immed    0x1000,gr10
+       set_gr_immed    63,gr11
+       dcpl            gr10,gr11,1
+       set_mem_immed   0x33333333,gr10
+       test_mem_immed  0x33333333,gr10
+
+       inc_gr_immed    0x1000,gr10
+       set_gr_immed    64,gr11
+       dcpl            gr10,gr11,1
+       set_mem_immed   0x44444444,gr10
+       test_mem_immed  0x44444444,gr10
+
+       ; Now write to another address which should be in the same set
+       ; the write should go through to memory, since all the lines in the
+       ; set are locked
+       inc_gr_immed    0x1000,gr10
+       set_mem_immed   0xdeadbeef,gr10
+       test_mem_immed  0xdeadbeef,gr10
+
+       ; Invalidate the data cache. Only the last value stored should have made
+       ; it through to memory
+       set_gr_immed    0x70000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0,gr10
+
+       inc_gr_immed    0x1000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0,gr10
+
+       inc_gr_immed    0x1000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0,gr10
+
+       inc_gr_immed    0x1000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0,gr10
+
+       inc_gr_immed    0x1000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0xdeadbeef,gr10
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/dcul.cgs b/sim/testsuite/sim/frv/fr500/dcul.cgs
new file mode 100644 (file)
index 0000000..4fd46f2
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/dcul.cgs
@@ -0,0 +1,118 @@
+# FRV testcase for dcul GRi
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global dcul
+dcul:
+       or_spr_immed    0xc8000000,hsr0 ; caches enabled -- copy-back mode
+
+       ; preload and lock all the lines in set 0 of the data cache
+       set_gr_immed    0x70000,gr10
+       lock_data_cache gr10
+       set_mem_immed   0x11111111,gr10
+       test_mem_immed  0x11111111,gr10
+
+       inc_gr_immed    0x1000,gr10
+       set_gr_immed    1,gr11
+       lock_data_cache gr10
+       set_mem_immed   0x22222222,gr10
+       test_mem_immed  0x22222222,gr10
+
+       inc_gr_immed    0x1000,gr10
+       set_gr_immed    63,gr11
+       lock_data_cache gr10
+       set_mem_immed   0x33333333,gr10
+       test_mem_immed  0x33333333,gr10
+
+       inc_gr_immed    0x1000,gr10
+       set_gr_immed    64,gr11
+       lock_data_cache gr10
+       set_mem_immed   0x44444444,gr10
+       test_mem_immed  0x44444444,gr10
+
+       ; Now write to another address which should be in the same set
+       ; the write should go through to memory, since all the lines in the
+       ; set are locked
+       inc_gr_immed    0x1000,gr10
+       set_mem_immed   0xdeadbeef,gr10
+       test_mem_immed  0xdeadbeef,gr10
+
+       ; Invalidate the data cache. Only the last value stored should have made
+       ; it through to memory
+       set_gr_immed    0x70000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0,gr10
+
+       inc_gr_immed    0x1000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0,gr10
+
+       inc_gr_immed    0x1000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0,gr10
+
+       inc_gr_immed    0x1000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0,gr10
+
+       inc_gr_immed    0x1000,gr10
+       invalidate_data_cache   gr10
+       test_mem_immed  0xdeadbeef,gr10
+
+       ; Now preload load and lock all the lines in set 0 of the data cache
+       ; again
+       set_gr_immed    0x70000,gr10
+       lock_data_cache gr10
+       set_mem_immed   0x11111111,gr10
+       test_mem_immed  0x11111111,gr10
+
+       inc_gr_immed    0x1000,gr10
+       set_gr_immed    1,gr11
+       lock_data_cache gr10
+       set_mem_immed   0x22222222,gr10
+       test_mem_immed  0x22222222,gr10
+
+       inc_gr_immed    0x1000,gr10
+       set_gr_immed    63,gr11
+       lock_data_cache gr10
+       set_mem_immed   0x33333333,gr10
+       test_mem_immed  0x33333333,gr10
+
+       inc_gr_immed    0x1000,gr10
+       set_gr_immed    64,gr11
+       lock_data_cache gr10
+       set_mem_immed   0x44444444,gr10
+       test_mem_immed  0x44444444,gr10
+
+       ; unlock one line
+       set_gr_immed    0x72000,gr10
+       dcul            gr10
+
+       ; Now write to another address which should be in the same set.
+       set_gr_immed    0x75000,gr10
+       set_mem_immed   0xbeefdead,gr10
+
+       ; All of the stored values should be retrievable
+
+       set_gr_immed    0x70000,gr10
+       test_mem_immed  0x11111111,gr10
+
+       inc_gr_immed    0x1000,gr10
+       test_mem_immed  0x22222222,gr10
+
+       inc_gr_immed    0x1000,gr10
+       test_mem_immed  0x33333333,gr10
+
+       inc_gr_immed    0x1000,gr10
+       test_mem_immed  0x44444444,gr10
+
+       inc_gr_immed    0x1000,gr10
+       test_mem_immed  0xdeadbeef,gr10
+
+       inc_gr_immed    0x1000,gr10
+       test_mem_immed  0xbeefdead,gr10
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/mclracc.cgs b/sim/testsuite/sim/frv/fr500/mclracc.cgs
new file mode 100644 (file)
index 0000000..c274d73
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/mclracc.cgs
@@ -0,0 +1,79 @@
+# frv testcase for mclracc $ACC40k,$A
+# mach: fr500
+
+       .include "../testutils.inc"
+
+       start
+
+       .global mclracc
+mclracc:
+       set_accg_immed  0xff,accg0
+       set_acc_immed   -1,acc0
+       set_accg_immed  0xff,accg1
+       set_acc_immed   -1,acc1
+       set_accg_immed  0xff,accg3
+       set_acc_immed   -1,acc3
+       set_accg_immed  0xff,accg7
+       set_acc_immed   -1,acc7
+
+       mclracc         acc8,0          ; nop
+       test_accg_immed 0xff,accg0
+       test_acc_immed  -1,acc0
+       test_accg_immed 0xff,accg1
+       test_acc_immed  -1,acc1
+       test_accg_immed 0xff,accg3
+       test_acc_immed  -1,acc3
+       test_accg_immed 0xff,accg7
+       test_acc_immed  -1,acc7
+
+       mclracc         acc8,1          ; nop
+       test_accg_immed 0xff,accg0
+       test_acc_immed  -1,acc0
+       test_accg_immed 0xff,accg1
+       test_acc_immed  -1,acc1
+       test_accg_immed 0xff,accg3
+       test_acc_immed  -1,acc3
+       test_accg_immed 0xff,accg7
+       test_acc_immed  -1,acc7
+
+       mclracc         acc3,0
+       test_accg_immed 0xff,accg0
+       test_acc_immed  -1,acc0
+       test_accg_immed 0xff,accg1
+       test_acc_immed  -1,acc1
+       test_accg_immed 0,accg3
+       test_acc_immed  0,acc3
+       test_accg_immed 0xff,accg7
+       test_acc_immed  -1,acc7
+
+       mclracc         acc7,1
+       test_accg_immed 0xff,accg0
+       test_acc_immed  -1,acc0
+       test_accg_immed 0xff,accg1
+       test_acc_immed  -1,acc1
+       test_accg_immed 0,accg3
+       test_acc_immed  0,acc3
+       test_accg_immed 0,accg7
+       test_acc_immed  0,acc7
+
+       mclracc         acc0,0
+       test_accg_immed 0,accg0
+       test_acc_immed  0,acc0
+       test_accg_immed 0xff,accg1
+       test_acc_immed  -1,acc1
+       test_accg_immed 0,accg3
+       test_acc_immed  0,acc3
+       test_accg_immed 0,accg7
+       test_acc_immed  0,acc7
+
+       mclracc         acc0,1
+       test_accg_immed 0,accg0
+       test_acc_immed  0,acc0
+       test_accg_immed 0,accg1
+       test_acc_immed  0,acc1
+       test_accg_immed 0,accg3
+       test_acc_immed  0,acc3
+       test_accg_immed 0,accg7
+       test_acc_immed  0,acc7
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/mqaddhss.cgs b/sim/testsuite/sim/frv/fr500/mqaddhss.cgs
new file mode 100644 (file)
index 0000000..23fb95a
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/mqaddhss.cgs
@@ -0,0 +1,79 @@
+# frv testcase for mqaddhss $FRi,$FRj,$FRj
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global mqaddhss
+mqaddhss:
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       mqaddhss        fr10,fr12,fr14
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0xbeef,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       mqaddhss        fr10,fr12,fr14
+       test_fr_limmed  0xbeef,0xdead,fr14
+       test_fr_limmed  0x2345,0x6789,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       mqaddhss        fr10,fr12,fr14
+       test_fr_limmed  0x1233,0x5677,fr14
+       test_fr_limmed  0x7fff,0x7fff,fr15
+       test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0xffff,0xfffe,fr12
+       set_fr_iimmed   0xfffe,0xfffe,fr13
+       mqaddhss        fr10,fr12,fr14
+       test_fr_limmed  0x8000,0x8000,fr14
+       test_fr_limmed  0x8000,0x8000,fr15
+       test_spr_bits   0x3c,2,0x7,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x7fff,0x0000,fr12
+       set_fr_iimmed   0x0000,0x8000,fr13
+       mqaddhss.p      fr10,fr10,fr14
+       mqaddhss        fr12,fr12,fr16
+       test_fr_limmed  0x0002,0x0002,fr14
+       test_fr_limmed  0xfffe,0xfffe,fr15
+       test_fr_limmed  0x7fff,0x0000,fr16
+       test_fr_limmed  0x0000,0x8000,fr17
+       test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie not set
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0x9,msr1         ; msr1.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/mqaddhus.cgs b/sim/testsuite/sim/frv/fr500/mqaddhus.cgs
new file mode 100644 (file)
index 0000000..ff08bf5
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/mqaddhus.cgs
@@ -0,0 +1,65 @@
+# frv testcase for mqaddhus $FRi,$FRj,$FRj
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global mqaddhus
+mqaddhus:
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       mqaddhus        fr10,fr12,fr14
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0xbeef,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       mqaddhus        fr10,fr12,fr14
+       test_fr_limmed  0xbeef,0xdead,fr14
+       test_fr_limmed  0x2345,0x6789,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x7ffe,0x7ffe,fr10
+       set_fr_iimmed   0xfffe,0xfffe,fr11
+       set_fr_iimmed   0x0002,0x0001,fr12
+       set_fr_iimmed   0x0001,0x0002,fr13
+       mqaddhus        fr10,fr12,fr14
+       test_fr_limmed  0x8000,0x7fff,fr14
+       test_fr_limmed  0xffff,0xffff,fr15
+       test_spr_bits   0x3c,2,1,msr0           ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf is set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0002,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0xfffe,0xfffe,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       mqaddhus.p      fr10,fr10,fr14
+       mqaddhus        fr12,fr12,fr16
+       test_fr_limmed  0x0004,0x0002,fr14
+       test_fr_limmed  0x0002,0x0002,fr15
+       test_fr_limmed  0xffff,0xffff,fr16
+       test_fr_limmed  0xffff,0xffff,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0xf,msr1         ; msr1.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/mqsubhss.cgs b/sim/testsuite/sim/frv/fr500/mqsubhss.cgs
new file mode 100644 (file)
index 0000000..a84f1fa
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/mqsubhss.cgs
@@ -0,0 +1,79 @@
+# frv testcase for mqsubhss $FRi,$FRj,$FRj
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global msubhss
+msubhss:
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0x0000,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0xbeef,fr13
+       mqsubhss        fr10,fr12,fr14
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0x4111,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x0000,0xdead,fr10
+       set_fr_iimmed   0x1234,0x5678,fr11
+       set_fr_iimmed   0xbeef,0x0000,fr12
+       set_fr_iimmed   0x1111,0x1111,fr13
+       mqsubhss        fr10,fr12,fr14
+       test_fr_limmed  0x4111,0xdead,fr14
+       test_fr_limmed  0x0123,0x4567,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0xffff,0xffff,fr12
+       set_fr_iimmed   0xfffe,0xffff,fr13
+       mqsubhss        fr10,fr12,fr14
+       test_fr_limmed  0x1235,0x5679,fr14
+       test_fr_limmed  0x7fff,0x7fff,fr15
+       test_spr_bits   0x3c,2,0x2,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x8001,0x8001,fr10
+       set_fr_iimmed   0x8001,0x8001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       mqsubhss        fr10,fr12,fr14
+       test_fr_limmed  0x8000,0x8000,fr14
+       test_fr_limmed  0x8000,0x8000,fr15
+       test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0xffff,0xffff,fr11
+       set_fr_iimmed   0x8000,0x8000,fr12
+       set_fr_iimmed   0x8000,0x8000,fr13
+       mqsubhss.p      fr10,fr10,fr14
+       mqsubhss        fr12,fr10,fr16
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0x0000,0x0000,fr15
+       test_fr_limmed  0x8000,0x8000,fr16
+       test_fr_limmed  0x8001,0x8001,fr17
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0xc,msr1         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       pass

diff --git a/sim/testsuite/sim/frv/fr500/mqsubhus.cgs b/sim/testsuite/sim/frv/fr500/mqsubhus.cgs
new file mode 100644 (file)
index 0000000..06dc01f
--- /dev/null
+++ b/sim/testsuite/sim/frv/fr500/mqsubhus.cgs
@@ -0,0 +1,66 @@
+# frv testcase for msubhus $FRi,$FRj,$FRj
+# mach: all
+
+       .include "../testutils.inc"
+
+       start
+
+       .global msubhus
+msubhus:
+       set_fr_iimmed   0x0000,0x0000,fr10
+       set_fr_iimmed   0xdead,0xbeef,fr11
+       set_fr_iimmed   0x0000,0x0000,fr12
+       set_fr_iimmed   0x0000,0x0000,fr13
+       mqsubhus        fr10,fr12,fr14
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0xdead,0xbeef,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_fr_iimmed   0x1234,0x5678,fr10
+       set_fr_iimmed   0x7ffe,0x7ffe,fr11
+       set_fr_iimmed   0x1111,0x1111,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       mqsubhus        fr10,fr12,fr14
+       test_fr_limmed  0x0123,0x4567,fr14
+       test_fr_limmed  0x7ffc,0x7ffd,fr15
+       test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
+       test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
+
+       set_spr_immed   0,msr0
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0001,0x0001,fr11
+       set_fr_iimmed   0x0001,0x0002,fr12
+       set_fr_iimmed   0x0002,0x0001,fr13
+       mqsubhus        fr10,fr12,fr14
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0x0000,0x0000,fr15
+       test_spr_bits   0x3c,2,0x6,msr0         ; msr0.sie is set
+       test_spr_bits   2,1,1,msr0              ; msr0.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       set_spr_immed   0,msr0
+       set_spr_immed   0,msr1
+       set_fr_iimmed   0x0001,0x0001,fr10
+       set_fr_iimmed   0x0002,0x0002,fr11
+       set_fr_iimmed   0x0000,0x0001,fr12
+       set_fr_iimmed   0x0002,0x0003,fr13
+       mqsubhus.p      fr10,fr10,fr14
+       mqsubhus        fr10,fr12,fr16
+       test_fr_limmed  0x0000,0x0000,fr14
+       test_fr_limmed  0x0000,0x0000,fr15
+       test_fr_limmed  0x0001,0x0000,fr16
+       test_fr_limmed  0x0000,0x0000,fr17
+       test_spr_bits   0x3c,2,0x0,msr0         ; msr0.sie is clear
+       test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
+       test_spr_bits   0x3c,2,0x1,msr1         ; msr1.sie is set
+       test_spr_bits   2,1,1,msr1              ; msr1.ovf set
+       test_spr_bits   1,0,1,msr0              ; msr0.aovf set
+       test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
+
+       pass