Stage 2 of structural changes for support of THUMB2. No logic changes.

diff --git a/vm/Android.mk b/vm/Android.mk
index 1fbe59b..8f873d4 100644 (file)
--- a/vm/Android.mk
+++ b/vm/Android.mk
@@ -266,11 +266,11 @@ ifeq ($(TARGET_ARCH),arm)
 
   ifeq ($(WITH_JIT),true)
     LOCAL_SRC_FILES += \
-               compiler/codegen/armv5te/Codegen-$(TARGET_ARCH_VARIANT).c \
-               compiler/codegen/armv5te/Assemble.c \
-               compiler/codegen/armv5te/ArchUtility.c \
-               compiler/codegen/armv5te/LocalOptimizations.c \
-               compiler/codegen/armv5te/GlobalOptimizations.c \
+               compiler/codegen/arm/Codegen-$(TARGET_ARCH_VARIANT).c \
+               compiler/codegen/arm/Assemble.c \
+               compiler/codegen/arm/ArchUtility.c \
+               compiler/codegen/arm/LocalOptimizations.c \
+               compiler/codegen/arm/GlobalOptimizations.c \
                compiler/template/out/CompilerTemplateAsm-$(TARGET_ARCH_VARIANT).S
   endif
 endif

diff --git a/vm/compiler/codegen/armv5te/ArchUtility.c b/vm/compiler/codegen/arm/ArchUtility.c
similarity index 90%
rename from vm/compiler/codegen/armv5te/ArchUtility.c
rename to vm/compiler/codegen/arm/ArchUtility.c
index d7a0ce6..6d1a261 100644 (file)
--- a/vm/compiler/codegen/armv5te/ArchUtility.c
+++ b/vm/compiler/codegen/arm/ArchUtility.c
@@ -16,7 +16,7 @@
 
 #include "../../CompilerInternals.h"
 #include "dexdump/OpCodeNames.h"
-#include "Armv5teLIR.h"
+#include "ArmLIR.h"
 
 /* Decode and print a ARM register name */
 static char * decodeRegList(int vector, char *buf)
@@ -41,7 +41,7 @@ static char * decodeRegList(int vector, char *buf)
  * Interpret a format string and build a string no longer than size
  * See format key in Assemble.c.
  */
-static void buildInsnString(char *fmt, Armv5teLIR *lir, char* buf,
+static void buildInsnString(char *fmt, ArmLIR *lir, char* buf,
                             unsigned char *baseAddr, int size)
 {
     int i;
@@ -151,7 +151,7 @@ static void buildInsnString(char *fmt, Armv5teLIR *lir, char* buf,
 /* Pretty-print a LIR instruction */
 static void dumpLIRInsn(LIR *arg, unsigned char *baseAddr)
 {
-    Armv5teLIR *lir = (Armv5teLIR *) arg;
+    ArmLIR *lir = (ArmLIR *) arg;
     char buf[256];
     char opName[256];
     int offset = lir->generic.offset;
@@ -159,40 +159,40 @@ static void dumpLIRInsn(LIR *arg, unsigned char *baseAddr)
     u2 *cPtr = (u2*)baseAddr;
     /* Handle pseudo-ops individually, and all regular insns as a group */
     switch(lir->opCode) {
-        case ARMV5TE_PSEUDO_TARGET_LABEL:
+        case ARM_PSEUDO_TARGET_LABEL:
             break;
-        case ARMV5TE_PSEUDO_CHAINING_CELL_NORMAL:
+        case ARM_PSEUDO_CHAINING_CELL_NORMAL:
             LOGD("-------- chaining cell (normal): 0x%04x\n", dest);
             break;
-        case ARMV5TE_PSEUDO_CHAINING_CELL_HOT:
+        case ARM_PSEUDO_CHAINING_CELL_HOT:
             LOGD("-------- chaining cell (hot): 0x%04x\n", dest);
             break;
-        case ARMV5TE_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED:
+        case ARM_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED:
             LOGD("-------- chaining cell (predicted)\n");
             break;
-        case ARMV5TE_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON:
+        case ARM_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON:
             LOGD("-------- chaining cell (invoke singleton): %s/%p\n",
                  ((Method *)dest)->name,
                  ((Method *)dest)->insns);
             break;
-        case ARMV5TE_PSEUDO_DALVIK_BYTECODE_BOUNDARY:
+        case ARM_PSEUDO_DALVIK_BYTECODE_BOUNDARY:
             LOGD("-------- dalvik offset: 0x%04x @ %s\n", dest,
                    getOpcodeName(lir->operands[1]));
             break;
-        case ARMV5TE_PSEUDO_ALIGN4:
+        case ARM_PSEUDO_ALIGN4:
             LOGD("%p (%04x): .align4\n", baseAddr + offset, offset);
             break;
-        case ARMV5TE_PSEUDO_PC_RECONSTRUCTION_CELL:
+        case ARM_PSEUDO_PC_RECONSTRUCTION_CELL:
             LOGD("-------- reconstruct dalvik PC : 0x%04x @ +0x%04x\n", dest,
                  lir->operands[1]);
             break;
-        case ARMV5TE_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL:
+        case ARM_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL:
             /* Do nothing */
             break;
-        case ARMV5TE_PSEUDO_EH_BLOCK_LABEL:
+        case ARM_PSEUDO_EH_BLOCK_LABEL:
             LOGD("Exception_Handling:\n");
             break;
-        case ARMV5TE_PSEUDO_NORMAL_BLOCK_LABEL:
+        case ARM_PSEUDO_NORMAL_BLOCK_LABEL:
             LOGD("L%#06x:\n", dest);
             break;
         default:
@@ -214,7 +214,7 @@ void dvmCompilerCodegenDump(CompilationUnit *cUnit)
 {
     LOGD("Dumping LIR insns\n");
     LIR *lirInsn;
-    Armv5teLIR *armLIR;
+    ArmLIR *armLIR;
 
     LOGD("installed code is at %p\n", cUnit->baseAddr);
     LOGD("total size is %d bytes\n", cUnit->totalSize);
@@ -222,7 +222,7 @@ void dvmCompilerCodegenDump(CompilationUnit *cUnit)
         dumpLIRInsn(lirInsn, cUnit->baseAddr);
     }
     for (lirInsn = cUnit->wordList; lirInsn; lirInsn = lirInsn->next) {
-        armLIR = (Armv5teLIR *) lirInsn;
+        armLIR = (ArmLIR *) lirInsn;
         LOGD("%p (%04x): .word (0x%x)\n",
              (char*)cUnit->baseAddr + armLIR->generic.offset, armLIR->generic.offset,
              armLIR->operands[0]);

diff --git a/vm/compiler/codegen/arm/ArmLIR.h b/vm/compiler/codegen/arm/ArmLIR.h
new file mode 100644 (file)
index 0000000..81e7346
--- /dev/null
+++ b/vm/compiler/codegen/arm/ArmLIR.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (C) 2009 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Dalvik.h"
+#include "compiler/CompilerInternals.h"
+
+#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMLIR_H
+#define _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMLIR_H
+
+/*
+ * r0, r1, r2, r3, and r7 are always scratch
+ * r4PC is scratch if used solely in the compiled land. Otherwise it holds the
+ * Dalvik PC.
+ * rFP holds the current frame pointer
+ * rGLUE holds &InterpState
+ */
+typedef enum NativeRegisterPool {
+    r0 = 0,
+    r1 = 1,
+    r2 = 2,
+    r3 = 3,
+    r4PC = 4,
+    rFP = 5,
+    rGLUE = 6,
+    r7 = 7,
+    r8 = 8,
+    r9 = 9,
+    r10 = 10,
+    r11 = 11,
+    r12 = 12,
+    r13 = 13,
+    rlr = 14,
+    rpc = 15
+} NativeRegisterPool;
+
+/* Mask to convert high reg to low for Thumb */
+#define THUMB_REG_MASK 0x7
+
+/* Thumb condition encodings */
+typedef enum ArmConditionCode {
+    ARM_COND_EQ = 0x0,    /* 0000 */
+    ARM_COND_NE = 0x1,    /* 0001 */
+    ARM_COND_LT = 0xb,    /* 1011 */
+    ARM_COND_GE = 0xa,    /* 1010 */
+    ARM_COND_GT = 0xc,    /* 1100 */
+    ARM_COND_LE = 0xd,    /* 1101 */
+    ARM_COND_CS = 0x2,    /* 0010 */
+    ARM_COND_MI = 0x4,    /* 0100 */
+} ArmConditionCode;
+
+#define isPseudoOpCode(opCode) ((int)(opCode) < 0)
+
+/*
+ * The following enum defines the list of supported Thumb instructions by the
+ * assembler. Their corresponding snippet positions will be defined in
+ * Assemble.c.
+ */
+typedef enum ArmOpCode {
+    ARM_PSEUDO_TARGET_LABEL = -11,
+    ARM_PSEUDO_CHAINING_CELL_HOT = -10,
+    ARM_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED = -9,
+    ARM_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON = -8,
+    ARM_PSEUDO_CHAINING_CELL_NORMAL = -7,
+    ARM_PSEUDO_DALVIK_BYTECODE_BOUNDARY = -6,
+    ARM_PSEUDO_ALIGN4 = -5,
+    ARM_PSEUDO_PC_RECONSTRUCTION_CELL = -4,
+    ARM_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL = -3,
+    ARM_PSEUDO_EH_BLOCK_LABEL = -2,
+    ARM_PSEUDO_NORMAL_BLOCK_LABEL = -1,
+    /************************************************************************/
+    ARM_16BIT_DATA,       /* DATA   [0] rd[15..0] */
+    THUMB_ADC,            /* adc     [0100000101] rm[5..3] rd[2..0] */
+    THUMB_ADD_RRI3,       /* add(1)  [0001110] imm_3[8..6] rn[5..3] rd[2..0]*/
+    THUMB_ADD_RI8,        /* add(2)  [00110] rd[10..8] imm_8[7..0] */
+    THUMB_ADD_RRR,        /* add(3)  [0001100] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_ADD_RR_LH,      /* add(4)  [01000100] H12[01] rm[5..3] rd[2..0] */
+    THUMB_ADD_RR_HL,      /* add(4)  [01001000] H12[10] rm[5..3] rd[2..0] */
+    THUMB_ADD_RR_HH,      /* add(4)  [01001100] H12[11] rm[5..3] rd[2..0] */
+    THUMB_ADD_PC_REL,     /* add(5)  [10100] rd[10..8] imm_8[7..0] */
+    THUMB_ADD_SP_REL,     /* add(6)  [10101] rd[10..8] imm_8[7..0] */
+    THUMB_ADD_SPI7,       /* add(7)  [101100000] imm_7[6..0] */
+    THUMB_AND_RR,         /* and     [0100000000] rm[5..3] rd[2..0] */
+    THUMB_ASR,            /* asr(1)  [00010] imm_5[10..6] rm[5..3] rd[2..0] */
+    THUMB_ASRV,           /* asr(2)  [0100000100] rs[5..3] rd[2..0] */
+    THUMB_B_COND,         /* b(1)    [1101] cond[11..8] offset_8[7..0] */
+    THUMB_B_UNCOND,       /* b(2)    [11100] offset_11[10..0] */
+    THUMB_BIC,            /* bic     [0100001110] rm[5..3] rd[2..0] */
+    THUMB_BKPT,           /* bkpt    [10111110] imm_8[7..0] */
+    THUMB_BLX_1,          /* blx(1)  [111] H[10] offset_11[10..0] */
+    THUMB_BLX_2,          /* blx(1)  [111] H[01] offset_11[10..0] */
+    THUMB_BL_1,           /* blx(1)  [111] H[10] offset_11[10..0] */
+    THUMB_BL_2,           /* blx(1)  [111] H[11] offset_11[10..0] */
+    THUMB_BLX_R,          /* blx(2)  [010001111] H2[6..6] rm[5..3] SBZ[000] */
+    THUMB_BX,             /* bx      [010001110] H2[6..6] rm[5..3] SBZ[000] */
+    THUMB_CMN,            /* cmn     [0100001011] rm[5..3] rd[2..0] */
+    THUMB_CMP_RI8,        /* cmp(1)  [00101] rn[10..8] imm_8[7..0] */
+    THUMB_CMP_RR,         /* cmp(2)  [0100001010] rm[5..3] rd[2..0] */
+    THUMB_CMP_LH,         /* cmp(3)  [01000101] H12[01] rm[5..3] rd[2..0] */
+    THUMB_CMP_HL,         /* cmp(3)  [01000110] H12[10] rm[5..3] rd[2..0] */
+    THUMB_CMP_HH,         /* cmp(3)  [01000111] H12[11] rm[5..3] rd[2..0] */
+    THUMB_EOR,            /* eor     [0100000001] rm[5..3] rd[2..0] */
+    THUMB_LDMIA,          /* ldmia   [11001] rn[10..8] reglist [7..0] */
+    THUMB_LDR_RRI5,       /* ldr(1)  [01101] imm_5[10..6] rn[5..3] rd[2..0] */
+    THUMB_LDR_RRR,        /* ldr(2)  [0101100] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_LDR_PC_REL,     /* ldr(3)  [01001] rd[10..8] imm_8[7..0] */
+    THUMB_LDR_SP_REL,     /* ldr(4)  [10011] rd[10..8] imm_8[7..0] */
+    THUMB_LDRB_RRI5,      /* ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0] */
+    THUMB_LDRB_RRR,       /* ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_LDRH_RRI5,      /* ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0] */
+    THUMB_LDRH_RRR,       /* ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_LDRSB_RRR,      /* ldrsb   [0101011] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_LDRSH_RRR,      /* ldrsh   [0101111] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_LSL,            /* lsl(1)  [00000] imm_5[10..6] rm[5..3] rd[2..0] */
+    THUMB_LSLV,           /* lsl(2)  [0100000010] rs[5..3] rd[2..0] */
+    THUMB_LSR,            /* lsr(1)  [00001] imm_5[10..6] rm[5..3] rd[2..0] */
+    THUMB_LSRV,           /* lsr(2)  [0100000011] rs[5..3] rd[2..0] */
+    THUMB_MOV_IMM,        /* mov(1)  [00100] rd[10..8] imm_8[7..0] */
+    THUMB_MOV_RR,         /* mov(2)  [0001110000] rn[5..3] rd[2..0] */
+    THUMB_MOV_RR_H2H,     /* mov(3)  [01000111] H12[11] rm[5..3] rd[2..0] */
+    THUMB_MOV_RR_H2L,     /* mov(3)  [01000110] H12[01] rm[5..3] rd[2..0] */
+    THUMB_MOV_RR_L2H,     /* mov(3)  [01000101] H12[10] rm[5..3] rd[2..0] */
+    THUMB_MUL,            /* mul     [0100001101] rm[5..3] rd[2..0] */
+    THUMB_MVN,            /* mvn     [0100001111] rm[5..3] rd[2..0] */
+    THUMB_NEG,            /* neg     [0100001001] rm[5..3] rd[2..0] */
+    THUMB_ORR,            /* orr     [0100001100] rm[5..3] rd[2..0] */
+    THUMB_POP,            /* pop     [1011110] r[8..8] rl[7..0] */
+    THUMB_PUSH,           /* push    [1011010] r[8..8] rl[7..0] */
+    THUMB_ROR,            /* ror     [0100000111] rs[5..3] rd[2..0] */
+    THUMB_SBC,            /* sbc     [0100000110] rm[5..3] rd[2..0] */
+    THUMB_STMIA,          /* stmia   [11000] rn[10..8] reglist [7.. 0] */
+    THUMB_STR_RRI5,       /* str(1)  [01100] imm_5[10..6] rn[5..3] rd[2..0] */
+    THUMB_STR_RRR,        /* str(2)  [0101000] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_STR_SP_REL,     /* str(3)  [10010] rd[10..8] imm_8[7..0] */
+    THUMB_STRB_RRI5,      /* strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0] */
+    THUMB_STRB_RRR,       /* strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_STRH_RRI5,      /* strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0] */
+    THUMB_STRH_RRR,       /* strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_SUB_RRI3,       /* sub(1)  [0001111] imm_3[8..6] rn[5..3] rd[2..0]*/
+    THUMB_SUB_RI8,        /* sub(2)  [00111] rd[10..8] imm_8[7..0] */
+    THUMB_SUB_RRR,        /* sub(3)  [0001101] rm[8..6] rn[5..3] rd[2..0] */
+    THUMB_SUB_SPI7,       /* sub(4)  [101100001] imm_7[6..0] */
+    THUMB_SWI,            /* swi     [11011111] imm_8[7..0] */
+    THUMB_TST,            /* tst     [0100001000] rm[5..3] rn[2..0] */
+    ARM_LAST,
+} ArmOpCode;
+
+/* Bit flags describing the behavior of each native opcode */
+typedef enum ArmOpFeatureFlags {
+    IS_BRANCH =           1 << 1,
+    CLOBBER_DEST =        1 << 2,
+    CLOBBER_SRC1 =        1 << 3,
+    NO_OPERAND =          1 << 4,
+    IS_UNARY_OP =         1 << 5,
+    IS_BINARY_OP =        1 << 6,
+    IS_TERTIARY_OP =      1 << 7,
+} ArmOpFeatureFlags;
+
+/* Struct used to define the snippet positions for each Thumb opcode */
+typedef struct ArmEncodingMap {
+    short skeleton;
+    struct {
+        int end;
+        int start;
+    } fieldLoc[3];
+    ArmOpCode opCode;
+    int flags;
+    char *name;
+    char* fmt;
+    int size;
+} ArmEncodingMap;
+
+extern ArmEncodingMap EncodingMap[ARM_LAST];
+
+/*
+ * Each instance of this struct holds a pseudo or real LIR instruction:
+ * - pesudo ones (eg labels and marks) and will be discarded by the assembler.
+ * - real ones will e assembled into Thumb instructions.
+ */
+typedef struct ArmLIR {
+    LIR generic;
+    ArmOpCode opCode;
+    int operands[3];    // [0..2] = [dest, src1, src2]
+    bool isNop;         // LIR is optimized away
+    int age;            // default is 0, set lazily by the optimizer
+    int size;           // 16-bit unit size (1 for thumb, 1 or 2 for thumb2)
+} ArmLIR;
+
+/* Chain cell for predicted method invocation */
+typedef struct PredictedChainingCell {
+    u4 branch;                  /* Branch to chained destination */
+    const ClassObject *clazz;   /* key #1 for prediction */
+    const Method *method;       /* key #2 to lookup native PC from dalvik PC */
+    u4 counter;                 /* counter to patch the chaining cell */
+} PredictedChainingCell;
+
+/* Init values when a predicted chain is initially assembled */
+#define PREDICTED_CHAIN_BX_PAIR_INIT     0
+#define PREDICTED_CHAIN_CLAZZ_INIT       0
+#define PREDICTED_CHAIN_METHOD_INIT      0
+#define PREDICTED_CHAIN_COUNTER_INIT     0
+
+/* Used when the callee is not compiled yet */
+#define PREDICTED_CHAIN_COUNTER_DELAY    16
+
+/* Rechain after this many mis-predictions have happened */
+#define PREDICTED_CHAIN_COUNTER_RECHAIN  1024
+
+/* Used if the resolved callee is a native method */
+#define PREDICTED_CHAIN_COUNTER_AVOID    0x7fffffff
+
+/* Utility macros to traverse the LIR/ArmLIR list */
+#define NEXT_LIR(lir) ((ArmLIR *) lir->generic.next)
+#define PREV_LIR(lir) ((ArmLIR *) lir->generic.prev)
+
+#define NEXT_LIR_LVALUE(lir) (lir)->generic.next
+#define PREV_LIR_LVALUE(lir) (lir)->generic.prev
+
+#define CHAIN_CELL_OFFSET_TAG   0xcdab
+
+#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMLIR_H */

diff --git a/vm/compiler/codegen/armv5te/Assemble.c b/vm/compiler/codegen/arm/Assemble.c
similarity index 83%
rename from vm/compiler/codegen/armv5te/Assemble.c
rename to vm/compiler/codegen/arm/Assemble.c
index f2f6e8c..f9961ce 100644 (file)
--- a/vm/compiler/codegen/armv5te/Assemble.c
+++ b/vm/compiler/codegen/arm/Assemble.c
@@ -19,11 +19,11 @@
 #include "dexdump/OpCodeNames.h"
 
 #include "../../CompilerInternals.h"
-#include "Armv5teLIR.h"
+#include "ArmLIR.h"
 #include <unistd.h>             /* for cacheflush */
 
 /*
- * opcode: Armv5teOpCode enum
+ * opcode: ArmOpCode enum
  * skeleton: pre-designated bit-pattern for this opcode
  * ds: dest start bit position
  * de: dest end bit position
@@ -63,226 +63,226 @@
  *
  *  [!] escape.  To insert "!", use "!!"
  */
-/* NOTE: must be kept in sync with enum Armv5teOpcode from Armv5teLIR.h */
-Armv5teEncodingMap EncodingMap[ARMV5TE_LAST] = {
-    ENCODING_MAP(ARMV5TE_16BIT_DATA,    0x0000, 15, 0, -1, -1, -1, -1,
+/* NOTE: must be kept in sync with enum ArmOpcode from ArmLIR.h */
+ArmEncodingMap EncodingMap[ARM_LAST] = {
+    ENCODING_MAP(ARM_16BIT_DATA,    0x0000, 15, 0, -1, -1, -1, -1,
                  IS_UNARY_OP,
                  "data", "0x!0h(!0d)", 1),
-    ENCODING_MAP(ARMV5TE_ADC,           0x4140, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_ADC,           0x4140, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "adc", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_ADD_RRI3,      0x1c00, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_ADD_RRI3,      0x1c00, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "add", "r!0d, r!1d, #!2d", 1),
-    ENCODING_MAP(ARMV5TE_ADD_RI8,       0x3000, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_ADD_RI8,       0x3000, 10, 8, 7, 0, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "add", "r!0d, r!0d, #!1d", 1),
-    ENCODING_MAP(ARMV5TE_ADD_RRR,       0x1800, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_ADD_RRR,       0x1800, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "add", "r!0d, r!1d, r!2d", 1),
-    ENCODING_MAP(ARMV5TE_ADD_RR_LH,     0x4440, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_ADD_RR_LH,     0x4440, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "add",
                  "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_ADD_RR_HL,     0x4480, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_ADD_RR_HL,     0x4480, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "add", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_ADD_RR_HH,     0x44c0, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_ADD_RR_HH,     0x44c0, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "add", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_ADD_PC_REL,    0xa000, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_ADD_PC_REL,    0xa000, 10, 8, 7, 0, -1, -1,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "add", "r!0d, pc, #!1E", 1),
-    ENCODING_MAP(ARMV5TE_ADD_SP_REL,    0xa800, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_ADD_SP_REL,    0xa800, 10, 8, 7, 0, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "add", "r!0d, sp, #!1E", 1),
-    ENCODING_MAP(ARMV5TE_ADD_SPI7,      0xb000, 6, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_ADD_SPI7,      0xb000, 6, 0, -1, -1, -1, -1,
                  IS_UNARY_OP | CLOBBER_DEST,
                  "add", "sp, #!0d*4", 1),
-    ENCODING_MAP(ARMV5TE_AND_RR,        0x4000, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_AND_RR,        0x4000, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "and", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_ASR,           0x1000, 2, 0, 5, 3, 10, 6,
+    ENCODING_MAP(THUMB_ASR,           0x1000, 2, 0, 5, 3, 10, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "asr", "r!0d, r!1d, #!2d", 1),
-    ENCODING_MAP(ARMV5TE_ASRV,          0x4100, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_ASRV,          0x4100, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "asr", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_B_COND,        0xd000, 7, 0, 11, 8, -1, -1,
+    ENCODING_MAP(THUMB_B_COND,        0xd000, 7, 0, 11, 8, -1, -1,
                  IS_BINARY_OP | IS_BRANCH,
                  "!1c", "!0t", 1),
-    ENCODING_MAP(ARMV5TE_B_UNCOND,      0xe000, 10, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_B_UNCOND,      0xe000, 10, 0, -1, -1, -1, -1,
                  NO_OPERAND | IS_BRANCH,
                  "b", "!0t", 1),
-    ENCODING_MAP(ARMV5TE_BIC,           0x4380, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_BIC,           0x4380, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "bic", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_BKPT,          0xbe00, 7, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_BKPT,          0xbe00, 7, 0, -1, -1, -1, -1,
                  IS_UNARY_OP | IS_BRANCH,
                  "bkpt", "!0d", 1),
-    ENCODING_MAP(ARMV5TE_BLX_1,         0xf000, 10, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_BLX_1,         0xf000, 10, 0, -1, -1, -1, -1,
                  IS_BINARY_OP | IS_BRANCH,
                  "blx_1", "!0u", 1),
-    ENCODING_MAP(ARMV5TE_BLX_2,         0xe800, 10, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_BLX_2,         0xe800, 10, 0, -1, -1, -1, -1,
                  IS_BINARY_OP | IS_BRANCH,
                  "blx_2", "!0v", 1),
-    ENCODING_MAP(ARMV5TE_BL_1,          0xf000, 10, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_BL_1,          0xf000, 10, 0, -1, -1, -1, -1,
                  IS_UNARY_OP | IS_BRANCH,
                  "bl_1", "!0u", 1),
-    ENCODING_MAP(ARMV5TE_BL_2,          0xf800, 10, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_BL_2,          0xf800, 10, 0, -1, -1, -1, -1,
                  IS_UNARY_OP | IS_BRANCH,
                  "bl_2", "!0v", 1),
-    ENCODING_MAP(ARMV5TE_BLX_R,         0x4780, 6, 3, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_BLX_R,         0x4780, 6, 3, -1, -1, -1, -1,
                  IS_UNARY_OP | IS_BRANCH,
                  "blx", "r!0d", 1),
-    ENCODING_MAP(ARMV5TE_BX,            0x4700, 6, 3, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_BX,            0x4700, 6, 3, -1, -1, -1, -1,
                  IS_UNARY_OP | IS_BRANCH,
                  "bx", "r!0d", 1),
-    ENCODING_MAP(ARMV5TE_CMN,           0x42c0, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_CMN,           0x42c0, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP,
                  "cmn", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_CMP_RI8,       0x2800, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_CMP_RI8,       0x2800, 10, 8, 7, 0, -1, -1,
                  IS_BINARY_OP,
                  "cmp", "r!0d, #!1d", 1),
-    ENCODING_MAP(ARMV5TE_CMP_RR,        0x4280, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_CMP_RR,        0x4280, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP,
                  "cmp", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_CMP_LH,        0x4540, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_CMP_LH,        0x4540, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP,
                  "cmp", "r!0d, r!1D", 1),
-    ENCODING_MAP(ARMV5TE_CMP_HL,        0x4580, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_CMP_HL,        0x4580, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP,
                  "cmp", "r!0D, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_CMP_HH,        0x45c0, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_CMP_HH,        0x45c0, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP,
                  "cmp", "r!0D, r!1D", 1),
-    ENCODING_MAP(ARMV5TE_EOR,           0x4040, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_EOR,           0x4040, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "eor", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_LDMIA,         0xc800, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_LDMIA,         0xc800, 10, 8, 7, 0, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST | CLOBBER_SRC1,
                  "ldmia", "r!0d!!, <!1R>", 1),
-    ENCODING_MAP(ARMV5TE_LDR_RRI5,      0x6800, 2, 0, 5, 3, 10, 6,
+    ENCODING_MAP(THUMB_LDR_RRI5,      0x6800, 2, 0, 5, 3, 10, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "ldr", "r!0d, [r!1d, #!2E]", 1),
-    ENCODING_MAP(ARMV5TE_LDR_RRR,       0x5800, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_LDR_RRR,       0x5800, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "ldr", "r!0d, [r!1d, r!2d]", 1),
-    ENCODING_MAP(ARMV5TE_LDR_PC_REL,    0x4800, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_LDR_PC_REL,    0x4800, 10, 8, 7, 0, -1, -1,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "ldr", "r!0d, [pc, #!1E]", 1),
-    ENCODING_MAP(ARMV5TE_LDR_SP_REL,    0x9800, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_LDR_SP_REL,    0x9800, 10, 8, 7, 0, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "ldr", "r!0d, [sp, #!1E]", 1),
-    ENCODING_MAP(ARMV5TE_LDRB_RRI5,     0x7800, 2, 0, 5, 3, 10, 6,
+    ENCODING_MAP(THUMB_LDRB_RRI5,     0x7800, 2, 0, 5, 3, 10, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "ldrb", "r!0d, [r!1d, #2d]", 1),
-    ENCODING_MAP(ARMV5TE_LDRB_RRR,      0x5c00, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_LDRB_RRR,      0x5c00, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "ldrb", "r!0d, [r!1d, r!2d]", 1),
-    ENCODING_MAP(ARMV5TE_LDRH_RRI5,     0x8800, 2, 0, 5, 3, 10, 6,
+    ENCODING_MAP(THUMB_LDRH_RRI5,     0x8800, 2, 0, 5, 3, 10, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "ldrh", "r!0d, [r!1d, #!2F]", 1),
-    ENCODING_MAP(ARMV5TE_LDRH_RRR,      0x5a00, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_LDRH_RRR,      0x5a00, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "ldrh", "r!0d, [r!1d, r!2d]", 1),
-    ENCODING_MAP(ARMV5TE_LDRSB_RRR,     0x5600, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_LDRSB_RRR,     0x5600, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "ldrsb", "r!0d, [r!1d, r!2d]", 1),
-    ENCODING_MAP(ARMV5TE_LDRSH_RRR,     0x5e00, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_LDRSH_RRR,     0x5e00, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "ldrsh", "r!0d, [r!1d, r!2d]", 1),
-    ENCODING_MAP(ARMV5TE_LSL,           0x0000, 2, 0, 5, 3, 10, 6,
+    ENCODING_MAP(THUMB_LSL,           0x0000, 2, 0, 5, 3, 10, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "lsl", "r!0d, r!1d, #!2d", 1),
-    ENCODING_MAP(ARMV5TE_LSLV,          0x4080, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_LSLV,          0x4080, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "lsl", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_LSR,           0x0800, 2, 0, 5, 3, 10, 6,
+    ENCODING_MAP(THUMB_LSR,           0x0800, 2, 0, 5, 3, 10, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "lsr", "r!0d, r!1d, #!2d", 1),
-    ENCODING_MAP(ARMV5TE_LSRV,          0x40c0, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_LSRV,          0x40c0, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "lsr", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_MOV_IMM,       0x2000, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_MOV_IMM,       0x2000, 10, 8, 7, 0, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "mov", "r!0d, #!1d", 1),
-    ENCODING_MAP(ARMV5TE_MOV_RR,        0x1c00, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_MOV_RR,        0x1c00, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "mov", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_MOV_RR_H2H,    0x46c0, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_MOV_RR_H2H,    0x46c0, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "mov", "r!0D, r!1D", 1),
-    ENCODING_MAP(ARMV5TE_MOV_RR_H2L,    0x4640, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_MOV_RR_H2L,    0x4640, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "mov", "r!0d, r!1D", 1),
-    ENCODING_MAP(ARMV5TE_MOV_RR_L2H,    0x4680, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_MOV_RR_L2H,    0x4680, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "mov", "r!0D, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_MUL,           0x4340, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_MUL,           0x4340, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "mul", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_MVN,           0x43c0, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_MVN,           0x43c0, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "mvn", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_NEG,           0x4240, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_NEG,           0x4240, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "neg", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_ORR,           0x4300, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_ORR,           0x4300, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "orr", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_POP,           0xbc00, 8, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_POP,           0xbc00, 8, 0, -1, -1, -1, -1,
                  IS_UNARY_OP,
                  "pop", "<!0R>", 1),
-    ENCODING_MAP(ARMV5TE_PUSH,          0xb400, 8, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_PUSH,          0xb400, 8, 0, -1, -1, -1, -1,
                  IS_UNARY_OP,
                  "push", "<!0R>", 1),
-    ENCODING_MAP(ARMV5TE_ROR,           0x41c0, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_ROR,           0x41c0, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "ror", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_SBC,           0x4180, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_SBC,           0x4180, 2, 0, 5, 3, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "sbc", "r!0d, r!1d", 1),
-    ENCODING_MAP(ARMV5TE_STMIA,         0xc000, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_STMIA,         0xc000, 10, 8, 7, 0, -1, -1,
                  IS_BINARY_OP | CLOBBER_SRC1,
                  "stmia", "r!0d!!, <!1R>", 1),
-    ENCODING_MAP(ARMV5TE_STR_RRI5,      0x6000, 2, 0, 5, 3, 10, 6,
+    ENCODING_MAP(THUMB_STR_RRI5,      0x6000, 2, 0, 5, 3, 10, 6,
                  IS_TERTIARY_OP,
                  "str", "r!0d, [r!1d, #!2E]", 1),
-    ENCODING_MAP(ARMV5TE_STR_RRR,       0x5000, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_STR_RRR,       0x5000, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP,
                  "str", "r!0d, [r!1d, r!2d]", 1),
-    ENCODING_MAP(ARMV5TE_STR_SP_REL,    0x9000, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_STR_SP_REL,    0x9000, 10, 8, 7, 0, -1, -1,
                  IS_BINARY_OP,
                  "str", "r!0d, [sp, #!1E]", 1),
-    ENCODING_MAP(ARMV5TE_STRB_RRI5,     0x7000, 2, 0, 5, 3, 10, 6,
+    ENCODING_MAP(THUMB_STRB_RRI5,     0x7000, 2, 0, 5, 3, 10, 6,
                  IS_TERTIARY_OP,
                  "strb", "r!0d, [r!1d, #!2d]", 1),
-    ENCODING_MAP(ARMV5TE_STRB_RRR,      0x5400, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_STRB_RRR,      0x5400, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP,
                  "strb", "r!0d, [r!1d, r!2d]", 1),
-    ENCODING_MAP(ARMV5TE_STRH_RRI5,     0x8000, 2, 0, 5, 3, 10, 6,
+    ENCODING_MAP(THUMB_STRH_RRI5,     0x8000, 2, 0, 5, 3, 10, 6,
                  IS_TERTIARY_OP,
                  "strh", "r!0d, [r!1d, #!2F]", 1),
-    ENCODING_MAP(ARMV5TE_STRH_RRR,      0x5200, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_STRH_RRR,      0x5200, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP,
                  "strh", "r!0d, [r!1d, r!2d]", 1),
-    ENCODING_MAP(ARMV5TE_SUB_RRI3,      0x1e00, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_SUB_RRI3,      0x1e00, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "sub", "r!0d, r!1d, #!2d]", 1),
-    ENCODING_MAP(ARMV5TE_SUB_RI8,       0x3800, 10, 8, 7, 0, -1, -1,
+    ENCODING_MAP(THUMB_SUB_RI8,       0x3800, 10, 8, 7, 0, -1, -1,
                  IS_BINARY_OP | CLOBBER_DEST,
                  "sub", "r!0d, #!1d", 1),
-    ENCODING_MAP(ARMV5TE_SUB_RRR,       0x1a00, 2, 0, 5, 3, 8, 6,
+    ENCODING_MAP(THUMB_SUB_RRR,       0x1a00, 2, 0, 5, 3, 8, 6,
                  IS_TERTIARY_OP | CLOBBER_DEST,
                  "sub", "r!0d, r!1d, r!2d", 1),
-    ENCODING_MAP(ARMV5TE_SUB_SPI7,      0xb080, 6, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_SUB_SPI7,      0xb080, 6, 0, -1, -1, -1, -1,
                  IS_UNARY_OP | CLOBBER_DEST,
                  "sub", "sp, #!0d", 1),
-    ENCODING_MAP(ARMV5TE_SWI,           0xdf00, 7, 0, -1, -1, -1, -1,
+    ENCODING_MAP(THUMB_SWI,           0xdf00, 7, 0, -1, -1, -1, -1,
                  IS_UNARY_OP | IS_BRANCH,
                  "swi", "!0d", 1),
-    ENCODING_MAP(ARMV5TE_TST,           0x4200, 2, 0, 5, 3, -1, -1,
+    ENCODING_MAP(THUMB_TST,           0x4200, 2, 0, 5, 3, -1, -1,
                  IS_UNARY_OP,
                  "tst", "r!0d, r!1d", 1),
 };
@@ -293,7 +293,7 @@ Armv5teEncodingMap EncodingMap[ARMV5TE_LAST] = {
 static void installDataContent(CompilationUnit *cUnit)
 {
     int *dataPtr = (int *) ((char *) cUnit->baseAddr + cUnit->dataOffset);
-    Armv5teLIR *dataLIR = (Armv5teLIR *) cUnit->wordList;
+    ArmLIR *dataLIR = (ArmLIR *) cUnit->wordList;
     while (dataLIR) {
         *dataPtr++ = dataLIR->operands[0];
         dataLIR = NEXT_LIR(dataLIR);
@@ -315,11 +315,11 @@ static int jitTraceDescriptionSize(const JitTraceDescription *desc)
 static bool assembleInstructions(CompilationUnit *cUnit, intptr_t startAddr)
 {
     short *bufferAddr = (short *) cUnit->codeBuffer;
-    Armv5teLIR *lir;
+    ArmLIR *lir;
 
-    for (lir = (Armv5teLIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
+    for (lir = (ArmLIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) {
         if (lir->opCode < 0) {
-            if ((lir->opCode == ARMV5TE_PSEUDO_ALIGN4) &&
+            if ((lir->opCode == ARM_PSEUDO_ALIGN4) &&
                 /* 1 means padding is needed */
                 (lir->operands[0] == 1)) {
                 *bufferAddr++ = PADDING_MOV_R0_R0;
@@ -331,9 +331,9 @@ static bool assembleInstructions(CompilationUnit *cUnit, intptr_t startAddr)
             continue;
         }
 
-        if (lir->opCode == ARMV5TE_LDR_PC_REL ||
-            lir->opCode == ARMV5TE_ADD_PC_REL) {
-            Armv5teLIR *lirTarget = (Armv5teLIR *) lir->generic.target;
+        if (lir->opCode == THUMB_LDR_PC_REL ||
+            lir->opCode == THUMB_ADD_PC_REL) {
+            ArmLIR *lirTarget = (ArmLIR *) lir->generic.target;
             intptr_t pc = (lir->generic.offset + 4) & ~3;
             /*
              * Allow an offset (stored in operands[2] to be added to the
@@ -350,8 +350,8 @@ static bool assembleInstructions(CompilationUnit *cUnit, intptr_t startAddr)
                 return true;
             }
             lir->operands[1] = delta >> 2;
-        } else if (lir->opCode == ARMV5TE_B_COND) {
-            Armv5teLIR *targetLIR = (Armv5teLIR *) lir->generic.target;
+        } else if (lir->opCode == THUMB_B_COND) {
+            ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
             intptr_t pc = lir->generic.offset + 4;
             intptr_t target = targetLIR->generic.offset;
             int delta = target - pc;
@@ -359,8 +359,8 @@ static bool assembleInstructions(CompilationUnit *cUnit, intptr_t startAddr)
                 return true;
             }
             lir->operands[0] = delta >> 1;
-        } else if (lir->opCode == ARMV5TE_B_UNCOND) {
-            Armv5teLIR *targetLIR = (Armv5teLIR *) lir->generic.target;
+        } else if (lir->opCode == THUMB_B_UNCOND) {
+            ArmLIR *targetLIR = (ArmLIR *) lir->generic.target;
             intptr_t pc = lir->generic.offset + 4;
             intptr_t target = targetLIR->generic.offset;
             int delta = target - pc;
@@ -369,8 +369,8 @@ static bool assembleInstructions(CompilationUnit *cUnit, intptr_t startAddr)
                 dvmAbort();
             }
             lir->operands[0] = delta >> 1;
-        } else if (lir->opCode == ARMV5TE_BLX_1) {
-            assert(NEXT_LIR(lir)->opCode == ARMV5TE_BLX_2);
+        } else if (lir->opCode == THUMB_BLX_1) {
+            assert(NEXT_LIR(lir)->opCode == THUMB_BLX_2);
             /* curPC is Thumb */
             intptr_t curPC = (startAddr + lir->generic.offset + 4) & ~3;
             intptr_t target = lir->operands[1];
@@ -386,7 +386,7 @@ static bool assembleInstructions(CompilationUnit *cUnit, intptr_t startAddr)
             NEXT_LIR(lir)->operands[0] = (delta>> 1) & 0x7ff;
         }
 
-        Armv5teEncodingMap *encoder = &EncodingMap[lir->opCode];
+        ArmEncodingMap *encoder = &EncodingMap[lir->opCode];
         short bits = encoder->skeleton;
         int i;
         for (i = 0; i < 3; i++) {
@@ -444,7 +444,7 @@ static bool assembleInstructions(CompilationUnit *cUnit, intptr_t startAddr)
 void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info)
 {
     LIR *lir;
-    Armv5teLIR *armLIR;
+    ArmLIR *armLIR;
     int offset = 0;
     int i;
     ChainCellCounts chainCellCounts;
@@ -454,13 +454,13 @@ void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info)
     info->instructionSet = cUnit->instructionSet;
 
     /* Beginning offset needs to allow space for chain cell offset */
-    for (armLIR = (Armv5teLIR *) cUnit->firstLIRInsn;
+    for (armLIR = (ArmLIR *) cUnit->firstLIRInsn;
          armLIR;
          armLIR = NEXT_LIR(armLIR)) {
         armLIR->generic.offset = offset;
         if (armLIR->opCode >= 0 && !armLIR->isNop) {
             offset += 2;
-        } else if (armLIR->opCode == ARMV5TE_PSEUDO_ALIGN4) {
+        } else if (armLIR->opCode == ARM_PSEUDO_ALIGN4) {
             if (offset & 0x2) {
                 offset += 2;
                 armLIR->operands[0] = 1;
@@ -476,10 +476,10 @@ void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info)
 
     /* Add space for chain cell counts & trace description */
     u4 chainCellOffset = offset;
-    Armv5teLIR *chainCellOffsetLIR = (Armv5teLIR *) cUnit->chainCellOffsetLIR;
+    ArmLIR *chainCellOffsetLIR = (ArmLIR *) cUnit->chainCellOffsetLIR;
     assert(chainCellOffsetLIR);
     assert(chainCellOffset < 0x10000);
-    assert(chainCellOffsetLIR->opCode == ARMV5TE_16BIT_DATA &&
+    assert(chainCellOffsetLIR->opCode == ARM_16BIT_DATA &&
            chainCellOffsetLIR->operands[0] == CHAIN_CELL_OFFSET_TAG);
 
     /*

diff --git a/vm/compiler/codegen/armv5te/Codegen-armv5te-vfp.c b/vm/compiler/codegen/arm/Codegen-armv5te-vfp.c
similarity index 97%
rename from vm/compiler/codegen/armv5te/Codegen-armv5te-vfp.c
rename to vm/compiler/codegen/arm/Codegen-armv5te-vfp.c
index 4e376ba..bbe7541 100644 (file)
--- a/vm/compiler/codegen/armv5te/Codegen-armv5te-vfp.c
+++ b/vm/compiler/codegen/arm/Codegen-armv5te-vfp.c
@@ -19,7 +19,7 @@
 #include "libdex/OpCode.h"
 #include "dexdump/OpCodeNames.h"
 #include "vm/compiler/CompilerInternals.h"
-#include "Armv5teLIR.h"
+#include "ArmLIR.h"
 #include "vm/mterp/common/FindInterface.h"
 
 #include "armv5te-vfp/ArchVariant.h"

diff --git a/vm/compiler/codegen/armv5te/Codegen-armv5te.c b/vm/compiler/codegen/arm/Codegen-armv5te.c
similarity index 97%
rename from vm/compiler/codegen/armv5te/Codegen-armv5te.c
rename to vm/compiler/codegen/arm/Codegen-armv5te.c
index 155c1ad..ba94d23 100644 (file)
--- a/vm/compiler/codegen/armv5te/Codegen-armv5te.c
+++ b/vm/compiler/codegen/arm/Codegen-armv5te.c
@@ -19,7 +19,7 @@
 #include "libdex/OpCode.h"
 #include "dexdump/OpCodeNames.h"
 #include "vm/compiler/CompilerInternals.h"
-#include "Armv5teLIR.h"
+#include "ArmLIR.h"
 #include "vm/mterp/common/FindInterface.h"
 
 #include "armv5te/ArchVariant.h"

diff --git a/vm/compiler/codegen/armv5te/Codegen-armv7-a.c b/vm/compiler/codegen/arm/Codegen-armv7-a.c
similarity index 97%
rename from vm/compiler/codegen/armv5te/Codegen-armv7-a.c
rename to vm/compiler/codegen/arm/Codegen-armv7-a.c
index 4e376ba..bbe7541 100644 (file)
--- a/vm/compiler/codegen/armv5te/Codegen-armv7-a.c
+++ b/vm/compiler/codegen/arm/Codegen-armv7-a.c
@@ -19,7 +19,7 @@
 #include "libdex/OpCode.h"
 #include "dexdump/OpCodeNames.h"
 #include "vm/compiler/CompilerInternals.h"
-#include "Armv5teLIR.h"
+#include "ArmLIR.h"
 #include "vm/mterp/common/FindInterface.h"
 
 #include "armv5te-vfp/ArchVariant.h"

diff --git a/vm/compiler/codegen/armv5te/Codegen.c b/vm/compiler/codegen/arm/Codegen.c
similarity index 83%
rename from vm/compiler/codegen/armv5te/Codegen.c
rename to vm/compiler/codegen/arm/Codegen.c
index b8f4da4..16779d9 100644 (file)
--- a/vm/compiler/codegen/armv5te/Codegen.c
+++ b/vm/compiler/codegen/arm/Codegen.c
@@ -56,19 +56,19 @@ static int opcodeCoverage[256];
  * The following are building blocks to construct low-level IRs with 0 - 3
  * operands.
  */
-static Armv5teLIR *newLIR0(CompilationUnit *cUnit, Armv5teOpCode opCode)
+static ArmLIR *newLIR0(CompilationUnit *cUnit, ArmOpCode opCode)
 {
-    Armv5teLIR *insn = dvmCompilerNew(sizeof(Armv5teLIR), true);
+    ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
     assert(isPseudoOpCode(opCode) || (EncodingMap[opCode].flags & NO_OPERAND));
     insn->opCode = opCode;
     dvmCompilerAppendLIR(cUnit, (LIR *) insn);
     return insn;
 }
 
-static Armv5teLIR *newLIR1(CompilationUnit *cUnit, Armv5teOpCode opCode,
+static ArmLIR *newLIR1(CompilationUnit *cUnit, ArmOpCode opCode,
                            int dest)
 {
-    Armv5teLIR *insn = dvmCompilerNew(sizeof(Armv5teLIR), true);
+    ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
     assert(isPseudoOpCode(opCode) || (EncodingMap[opCode].flags & IS_UNARY_OP));
     insn->opCode = opCode;
     insn->operands[0] = dest;
@@ -76,10 +76,10 @@ static Armv5teLIR *newLIR1(CompilationUnit *cUnit, Armv5teOpCode opCode,
     return insn;
 }
 
-static Armv5teLIR *newLIR2(CompilationUnit *cUnit, Armv5teOpCode opCode,
+static ArmLIR *newLIR2(CompilationUnit *cUnit, ArmOpCode opCode,
                            int dest, int src1)
 {
-    Armv5teLIR *insn = dvmCompilerNew(sizeof(Armv5teLIR), true);
+    ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
     assert(isPseudoOpCode(opCode) ||
            (EncodingMap[opCode].flags & IS_BINARY_OP));
     insn->opCode = opCode;
@@ -89,10 +89,10 @@ static Armv5teLIR *newLIR2(CompilationUnit *cUnit, Armv5teOpCode opCode,
     return insn;
 }
 
-static Armv5teLIR *newLIR3(CompilationUnit *cUnit, Armv5teOpCode opCode,
+static ArmLIR *newLIR3(CompilationUnit *cUnit, ArmOpCode opCode,
                            int dest, int src1, int src2)
 {
-    Armv5teLIR *insn = dvmCompilerNew(sizeof(Armv5teLIR), true);
+    ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true);
     assert(isPseudoOpCode(opCode) ||
            (EncodingMap[opCode].flags & IS_TERTIARY_OP));
     insn->opCode = opCode;
@@ -103,7 +103,7 @@ static Armv5teLIR *newLIR3(CompilationUnit *cUnit, Armv5teOpCode opCode,
     return insn;
 }
 
-static Armv5teLIR *newLIR23(CompilationUnit *cUnit, Armv5teOpCode opCode,
+static ArmLIR *newLIR23(CompilationUnit *cUnit, ArmOpCode opCode,
                             int srcdest, int src2)
 {
     assert(!isPseudoOpCode(opCode));
@@ -195,19 +195,19 @@ static inline int selectFirstRegister(CompilationUnit *cUnit, int vSrc,
  */
 
 /* Add a 32-bit constant either in the constant pool or mixed with code */
-static Armv5teLIR *addWordData(CompilationUnit *cUnit, int value, bool inPlace)
+static ArmLIR *addWordData(CompilationUnit *cUnit, int value, bool inPlace)
 {
     /* Add the constant to the literal pool */
     if (!inPlace) {
-        Armv5teLIR *newValue = dvmCompilerNew(sizeof(Armv5teLIR), true);
+        ArmLIR *newValue = dvmCompilerNew(sizeof(ArmLIR), true);
         newValue->operands[0] = value;
         newValue->generic.next = cUnit->wordList;
         cUnit->wordList = (LIR *) newValue;
         return newValue;
     } else {
         /* Add the constant in the middle of code stream */
-        newLIR1(cUnit, ARMV5TE_16BIT_DATA, (value & 0xffff));
-        newLIR1(cUnit, ARMV5TE_16BIT_DATA, (value >> 16));
+        newLIR1(cUnit, ARM_16BIT_DATA, (value & 0xffff));
+        newLIR1(cUnit, ARM_16BIT_DATA, (value >> 16));
     }
     return NULL;
 }
@@ -216,14 +216,14 @@ static Armv5teLIR *addWordData(CompilationUnit *cUnit, int value, bool inPlace)
  * Search the existing constants in the literal pool for an exact or close match
  * within specified delta (greater or equal to 0).
  */
-static Armv5teLIR *scanLiteralPool(CompilationUnit *cUnit, int value,
+static ArmLIR *scanLiteralPool(CompilationUnit *cUnit, int value,
                                    unsigned int delta)
 {
     LIR *dataTarget = cUnit->wordList;
     while (dataTarget) {
-        if (((unsigned) (value - ((Armv5teLIR *) dataTarget)->operands[0])) <=
+        if (((unsigned) (value - ((ArmLIR *) dataTarget)->operands[0])) <=
             delta)
-            return (Armv5teLIR *) dataTarget;
+            return (ArmLIR *) dataTarget;
         dataTarget = dataTarget->next;
     }
     return NULL;
@@ -237,20 +237,20 @@ void loadConstant(CompilationUnit *cUnit, int rDest, int value)
 {
     /* See if the value can be constructed cheaply */
     if ((value >= 0) && (value <= 255)) {
-        newLIR2(cUnit, ARMV5TE_MOV_IMM, rDest, value);
+        newLIR2(cUnit, THUMB_MOV_IMM, rDest, value);
         return;
     } else if ((value & 0xFFFFFF00) == 0xFFFFFF00) {
-        newLIR2(cUnit, ARMV5TE_MOV_IMM, rDest, ~value);
-        newLIR2(cUnit, ARMV5TE_MVN, rDest, rDest);
+        newLIR2(cUnit, THUMB_MOV_IMM, rDest, ~value);
+        newLIR2(cUnit, THUMB_MVN, rDest, rDest);
         return;
     }
     /* No shortcut - go ahead and use literal pool */
-    Armv5teLIR *dataTarget = scanLiteralPool(cUnit, value, 255);
+    ArmLIR *dataTarget = scanLiteralPool(cUnit, value, 255);
     if (dataTarget == NULL) {
         dataTarget = addWordData(cUnit, value, false);
     }
-    Armv5teLIR *loadPcRel = dvmCompilerNew(sizeof(Armv5teLIR), true);
-    loadPcRel->opCode = ARMV5TE_LDR_PC_REL;
+    ArmLIR *loadPcRel = dvmCompilerNew(sizeof(ArmLIR), true);
+    loadPcRel->opCode = THUMB_LDR_PC_REL;
     loadPcRel->generic.target = (LIR *) dataTarget;
     loadPcRel->operands[0] = rDest;
     dvmCompilerAppendLIR(cUnit, (LIR *) loadPcRel);
@@ -260,7 +260,7 @@ void loadConstant(CompilationUnit *cUnit, int rDest, int value)
      * add up to 255 to an existing constant value.
      */
     if (dataTarget->operands[0] != value) {
-        newLIR2(cUnit, ARMV5TE_ADD_RI8, rDest, value - dataTarget->operands[0]);
+        newLIR2(cUnit, THUMB_ADD_RI8, rDest, value - dataTarget->operands[0]);
     }
 }
 
@@ -269,24 +269,24 @@ static void genExportPC(CompilationUnit *cUnit, MIR *mir, int rDPC, int rAddr)
 {
     int offset = offsetof(StackSaveArea, xtra.currentPc);
     loadConstant(cUnit, rDPC, (int) (cUnit->method->insns + mir->offset));
-    newLIR2(cUnit, ARMV5TE_MOV_RR, rAddr, rFP);
-    newLIR2(cUnit, ARMV5TE_SUB_RI8, rAddr, sizeof(StackSaveArea) - offset);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, rDPC, rAddr, 0);
+    newLIR2(cUnit, THUMB_MOV_RR, rAddr, rFP);
+    newLIR2(cUnit, THUMB_SUB_RI8, rAddr, sizeof(StackSaveArea) - offset);
+    newLIR3(cUnit, THUMB_STR_RRI5, rDPC, rAddr, 0);
 }
 
 /* Generate conditional branch instructions */
 static void genConditionalBranch(CompilationUnit *cUnit,
-                                 Armv5teConditionCode cond,
-                                 Armv5teLIR *target)
+                                 ArmConditionCode cond,
+                                 ArmLIR *target)
 {
-    Armv5teLIR *branch = newLIR2(cUnit, ARMV5TE_B_COND, 0, cond);
+    ArmLIR *branch = newLIR2(cUnit, THUMB_B_COND, 0, cond);
     branch->generic.target = (LIR *) target;
 }
 
 /* Generate unconditional branch instructions */
-static void genUnconditionalBranch(CompilationUnit *cUnit, Armv5teLIR *target)
+static void genUnconditionalBranch(CompilationUnit *cUnit, ArmLIR *target)
 {
-    Armv5teLIR *branch = newLIR0(cUnit, ARMV5TE_B_UNCOND);
+    ArmLIR *branch = newLIR0(cUnit, THUMB_B_UNCOND);
     branch->generic.target = (LIR *) target;
 }
 
@@ -298,10 +298,10 @@ static void genReturnCommon(CompilationUnit *cUnit, MIR *mir)
     gDvmJit.returnOp++;
 #endif
     int dPC = (int) (cUnit->method->insns + mir->offset);
-    Armv5teLIR *branch = newLIR0(cUnit, ARMV5TE_B_UNCOND);
+    ArmLIR *branch = newLIR0(cUnit, THUMB_B_UNCOND);
     /* Set up the place holder to reconstruct this Dalvik PC */
-    Armv5teLIR *pcrLabel = dvmCompilerNew(sizeof(Armv5teLIR), true);
-    pcrLabel->opCode = ARMV5TE_PSEUDO_PC_RECONSTRUCTION_CELL;
+    ArmLIR *pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
+    pcrLabel->opCode = ARM_PSEUDO_PC_RECONSTRUCTION_CELL;
     pcrLabel->operands[0] = dPC;
     pcrLabel->operands[1] = mir->offset;
     /* Insert the place holder to the growable list */
@@ -319,20 +319,20 @@ static void loadValuePair(CompilationUnit *cUnit, int vSrc, int rDestLo,
 {
     /* Use reg + imm5*4 to load the values if possible */
     if (vSrc <= 30) {
-        newLIR3(cUnit, ARMV5TE_LDR_RRI5, rDestLo, rFP, vSrc);
-        newLIR3(cUnit, ARMV5TE_LDR_RRI5, rDestHi, rFP, vSrc+1);
+        newLIR3(cUnit, THUMB_LDR_RRI5, rDestLo, rFP, vSrc);
+        newLIR3(cUnit, THUMB_LDR_RRI5, rDestHi, rFP, vSrc+1);
     } else {
         if (vSrc <= 64) {
             /* Sneak 4 into the base address first */
-            newLIR3(cUnit, ARMV5TE_ADD_RRI3, rDestLo, rFP, 4);
-            newLIR2(cUnit, ARMV5TE_ADD_RI8, rDestLo, (vSrc-1)*4);
+            newLIR3(cUnit, THUMB_ADD_RRI3, rDestLo, rFP, 4);
+            newLIR2(cUnit, THUMB_ADD_RI8, rDestLo, (vSrc-1)*4);
         } else {
             /* Offset too far from rFP */
             loadConstant(cUnit, rDestLo, vSrc*4);
-            newLIR3(cUnit, ARMV5TE_ADD_RRR, rDestLo, rFP, rDestLo);
+            newLIR3(cUnit, THUMB_ADD_RRR, rDestLo, rFP, rDestLo);
         }
         assert(rDestLo < rDestHi);
-        newLIR2(cUnit, ARMV5TE_LDMIA, rDestLo, (1<<rDestLo) | (1<<(rDestHi)));
+        newLIR2(cUnit, THUMB_LDMIA, rDestLo, (1<<rDestLo) | (1<<(rDestHi)));
     }
 }
 
@@ -349,20 +349,20 @@ static void storeValuePair(CompilationUnit *cUnit, int rSrcLo, int rSrcHi,
 
     /* Use reg + imm5*4 to store the values if possible */
     if (vDest <= 30) {
-        newLIR3(cUnit, ARMV5TE_STR_RRI5, rSrcLo, rFP, vDest);
-        newLIR3(cUnit, ARMV5TE_STR_RRI5, rSrcHi, rFP, vDest+1);
+        newLIR3(cUnit, THUMB_STR_RRI5, rSrcLo, rFP, vDest);
+        newLIR3(cUnit, THUMB_STR_RRI5, rSrcHi, rFP, vDest+1);
     } else {
         if (vDest <= 64) {
             /* Sneak 4 into the base address first */
-            newLIR3(cUnit, ARMV5TE_ADD_RRI3, rScratch, rFP, 4);
-            newLIR2(cUnit, ARMV5TE_ADD_RI8, rScratch, (vDest-1)*4);
+            newLIR3(cUnit, THUMB_ADD_RRI3, rScratch, rFP, 4);
+            newLIR2(cUnit, THUMB_ADD_RI8, rScratch, (vDest-1)*4);
         } else {
             /* Offset too far from rFP */
             loadConstant(cUnit, rScratch, vDest*4);
-            newLIR3(cUnit, ARMV5TE_ADD_RRR, rScratch, rFP, rScratch);
+            newLIR3(cUnit, THUMB_ADD_RRR, rScratch, rFP, rScratch);
         }
         assert(rSrcLo < rSrcHi);
-        newLIR2(cUnit, ARMV5TE_STMIA, rScratch, (1<<rSrcLo) | (1 << (rSrcHi)));
+        newLIR2(cUnit, THUMB_STMIA, rScratch, (1<<rSrcLo) | (1 << (rSrcHi)));
     }
 }
 
@@ -371,14 +371,14 @@ static void loadValueAddress(CompilationUnit *cUnit, int vSrc, int rDest)
 {
     /* RRI3 can add up to 7 */
     if (vSrc <= 1) {
-        newLIR3(cUnit, ARMV5TE_ADD_RRI3, rDest, rFP, vSrc*4);
+        newLIR3(cUnit, THUMB_ADD_RRI3, rDest, rFP, vSrc*4);
     } else if (vSrc <= 64) {
         /* Sneak 4 into the base address first */
-        newLIR3(cUnit, ARMV5TE_ADD_RRI3, rDest, rFP, 4);
-        newLIR2(cUnit, ARMV5TE_ADD_RI8, rDest, (vSrc-1)*4);
+        newLIR3(cUnit, THUMB_ADD_RRI3, rDest, rFP, 4);
+        newLIR2(cUnit, THUMB_ADD_RI8, rDest, (vSrc-1)*4);
     } else {
         loadConstant(cUnit, rDest, vSrc*4);
-        newLIR3(cUnit, ARMV5TE_ADD_RRR, rDest, rFP, rDest);
+        newLIR3(cUnit, THUMB_ADD_RRR, rDest, rFP, rDest);
     }
 }
 
@@ -387,10 +387,10 @@ static void loadValue(CompilationUnit *cUnit, int vSrc, int rDest)
 {
     /* Use reg + imm5*4 to load the value if possible */
     if (vSrc <= 31) {
-        newLIR3(cUnit, ARMV5TE_LDR_RRI5, rDest, rFP, vSrc);
+        newLIR3(cUnit, THUMB_LDR_RRI5, rDest, rFP, vSrc);
     } else {
         loadConstant(cUnit, rDest, vSrc*4);
-        newLIR3(cUnit, ARMV5TE_LDR_RRR, rDest, rFP, rDest);
+        newLIR3(cUnit, THUMB_LDR_RRR, rDest, rFP, rDest);
     }
 }
 
@@ -401,10 +401,10 @@ static void loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
     assert((displacement & 0x3) == 0);
     /* Can it fit in a RRI5? */
     if (displacement < 128) {
-        newLIR3(cUnit, ARMV5TE_LDR_RRI5, rDest, rBase, displacement >> 2);
+        newLIR3(cUnit, THUMB_LDR_RRI5, rDest, rBase, displacement >> 2);
     } else {
         loadConstant(cUnit, rDest, displacement);
-        newLIR3(cUnit, ARMV5TE_LDR_RRR, rDest, rBase, rDest);
+        newLIR3(cUnit, THUMB_LDR_RRR, rDest, rBase, rDest);
     }
 }
 
@@ -417,10 +417,10 @@ static void storeValue(CompilationUnit *cUnit, int rSrc, int vDest,
 
     /* Use reg + imm5*4 to store the value if possible */
     if (vDest <= 31) {
-        newLIR3(cUnit, ARMV5TE_STR_RRI5, rSrc, rFP, vDest);
+        newLIR3(cUnit, THUMB_STR_RRI5, rSrc, rFP, vDest);
     } else {
         loadConstant(cUnit, rScratch, vDest*4);
-        newLIR3(cUnit, ARMV5TE_STR_RRR, rSrc, rFP, rScratch);
+        newLIR3(cUnit, THUMB_STR_RRR, rSrc, rFP, rScratch);
     }
 }
 
@@ -429,7 +429,7 @@ static void storeValue(CompilationUnit *cUnit, int rSrc, int vDest,
  * r0/r1 pair.
  */
 static void genBinaryOpWide(CompilationUnit *cUnit, int vDest,
-                            Armv5teOpCode preinst, Armv5teOpCode inst,
+                            ArmOpCode preinst, ArmOpCode inst,
                             int reg0, int reg2)
 {
     int reg1 = NEXT_REG(reg0);
@@ -440,7 +440,7 @@ static void genBinaryOpWide(CompilationUnit *cUnit, int vDest,
 }
 
 /* Perform a binary operation on 32-bit operands and leave the results in r0. */
-static void genBinaryOp(CompilationUnit *cUnit, int vDest, Armv5teOpCode inst,
+static void genBinaryOp(CompilationUnit *cUnit, int vDest, ArmOpCode inst,
                         int reg0, int reg1, int regDest)
 {
     if (EncodingMap[inst].flags & IS_BINARY_OP) {
@@ -453,15 +453,15 @@ static void genBinaryOp(CompilationUnit *cUnit, int vDest, Armv5teOpCode inst,
 }
 
 /* Create the PC reconstruction slot if not already done */
-static inline Armv5teLIR *genCheckCommon(CompilationUnit *cUnit, int dOffset,
-                                         Armv5teLIR *branch,
-                                         Armv5teLIR *pcrLabel)
+static inline ArmLIR *genCheckCommon(CompilationUnit *cUnit, int dOffset,
+                                         ArmLIR *branch,
+                                         ArmLIR *pcrLabel)
 {
     /* Set up the place holder to reconstruct this Dalvik PC */
     if (pcrLabel == NULL) {
         int dPC = (int) (cUnit->method->insns + dOffset);
-        pcrLabel = dvmCompilerNew(sizeof(Armv5teLIR), true);
-        pcrLabel->opCode = ARMV5TE_PSEUDO_PC_RECONSTRUCTION_CELL;
+        pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
+        pcrLabel->opCode = ARM_PSEUDO_PC_RECONSTRUCTION_CELL;
         pcrLabel->operands[0] = dPC;
         pcrLabel->operands[1] = dOffset;
         /* Insert the place holder to the growable list */
@@ -476,13 +476,13 @@ static inline Armv5teLIR *genCheckCommon(CompilationUnit *cUnit, int dOffset,
  * Perform a "reg cmp imm" operation and jump to the PCR region if condition
  * satisfies.
  */
-static inline Armv5teLIR *genRegImmCheck(CompilationUnit *cUnit,
-                                         Armv5teConditionCode cond, int reg,
+static inline ArmLIR *genRegImmCheck(CompilationUnit *cUnit,
+                                         ArmConditionCode cond, int reg,
                                          int checkValue, int dOffset,
-                                         Armv5teLIR *pcrLabel)
+                                         ArmLIR *pcrLabel)
 {
-    newLIR2(cUnit, ARMV5TE_CMP_RI8, reg, checkValue);
-    Armv5teLIR *branch = newLIR2(cUnit, ARMV5TE_B_COND, 0, cond);
+    newLIR2(cUnit, THUMB_CMP_RI8, reg, checkValue);
+    ArmLIR *branch = newLIR2(cUnit, THUMB_B_COND, 0, cond);
     return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
 }
 
@@ -490,13 +490,13 @@ static inline Armv5teLIR *genRegImmCheck(CompilationUnit *cUnit,
  * Perform a "reg cmp reg" operation and jump to the PCR region if condition
  * satisfies.
  */
-static inline Armv5teLIR *inertRegRegCheck(CompilationUnit *cUnit,
-                                           Armv5teConditionCode cond,
+static inline ArmLIR *inertRegRegCheck(CompilationUnit *cUnit,
+                                           ArmConditionCode cond,
                                            int reg1, int reg2, int dOffset,
-                                           Armv5teLIR *pcrLabel)
+                                           ArmLIR *pcrLabel)
 {
-    newLIR2(cUnit, ARMV5TE_CMP_RR, reg1, reg2);
-    Armv5teLIR *branch = newLIR2(cUnit, ARMV5TE_B_COND, 0, cond);
+    newLIR2(cUnit, THUMB_CMP_RR, reg1, reg2);
+    ArmLIR *branch = newLIR2(cUnit, THUMB_B_COND, 0, cond);
     return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
 }
 
@@ -505,8 +505,8 @@ static inline Armv5teLIR *inertRegRegCheck(CompilationUnit *cUnit,
  * and mReg is the machine register holding the actual value. If internal state
  * indicates that vReg has been checked before the check request is ignored.
  */
-static Armv5teLIR *genNullCheck(CompilationUnit *cUnit, int vReg, int mReg,
-                                int dOffset, Armv5teLIR *pcrLabel)
+static ArmLIR *genNullCheck(CompilationUnit *cUnit, int vReg, int mReg,
+                                int dOffset, ArmLIR *pcrLabel)
 {
     /* This particular Dalvik register has been null-checked */
     if (dvmIsBitSet(cUnit->registerScoreboard.nullCheckedRegs, vReg)) {
@@ -520,25 +520,25 @@ static Armv5teLIR *genNullCheck(CompilationUnit *cUnit, int vReg, int mReg,
  * Perform zero-check on a register. Similar to genNullCheck but the value being
  * checked does not have a corresponding Dalvik register.
  */
-static Armv5teLIR *genZeroCheck(CompilationUnit *cUnit, int mReg,
-                                int dOffset, Armv5teLIR *pcrLabel)
+static ArmLIR *genZeroCheck(CompilationUnit *cUnit, int mReg,
+                                int dOffset, ArmLIR *pcrLabel)
 {
     return genRegImmCheck(cUnit, ARM_COND_EQ, mReg, 0, dOffset, pcrLabel);
 }
 
 /* Perform bound check on two registers */
-static Armv5teLIR *genBoundsCheck(CompilationUnit *cUnit, int rIndex,
-                                  int rBound, int dOffset, Armv5teLIR *pcrLabel)
+static ArmLIR *genBoundsCheck(CompilationUnit *cUnit, int rIndex,
+                                  int rBound, int dOffset, ArmLIR *pcrLabel)
 {
     return inertRegRegCheck(cUnit, ARM_COND_CS, rIndex, rBound, dOffset,
                             pcrLabel);
 }
 
 /* Generate a unconditional branch to go to the interpreter */
-static inline Armv5teLIR *genTrap(CompilationUnit *cUnit, int dOffset,
-                                  Armv5teLIR *pcrLabel)
+static inline ArmLIR *genTrap(CompilationUnit *cUnit, int dOffset,
+                                  ArmLIR *pcrLabel)
 {
-    Armv5teLIR *branch = newLIR0(cUnit, ARMV5TE_B_UNCOND);
+    ArmLIR *branch = newLIR0(cUnit, THUMB_B_UNCOND);
     return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
 }
 
@@ -563,8 +563,8 @@ static void genIGetWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
     loadValue(cUnit, dInsn->vB, reg2);
     loadConstant(cUnit, reg3, fieldOffset);
     genNullCheck(cUnit, dInsn->vB, reg2, mir->offset, NULL); /* null object? */
-    newLIR3(cUnit, ARMV5TE_ADD_RRR, reg2, reg2, reg3);
-    newLIR2(cUnit, ARMV5TE_LDMIA, reg2, (1<<reg0 | 1<<reg1));
+    newLIR3(cUnit, THUMB_ADD_RRR, reg2, reg2, reg3);
+    newLIR2(cUnit, THUMB_LDMIA, reg2, (1<<reg0 | 1<<reg1));
     storeValuePair(cUnit, reg0, reg1, dInsn->vA, reg3);
 }
 
@@ -592,21 +592,21 @@ static void genIPutWide(CompilationUnit *cUnit, MIR *mir, int fieldOffset)
     updateLiveRegisterPair(cUnit, dInsn->vA, reg0, reg1);
     loadConstant(cUnit, reg3, fieldOffset);
     genNullCheck(cUnit, dInsn->vB, reg2, mir->offset, NULL); /* null object? */
-    newLIR3(cUnit, ARMV5TE_ADD_RRR, reg2, reg2, reg3);
-    newLIR2(cUnit, ARMV5TE_STMIA, reg2, (1<<reg0 | 1<<reg1));
+    newLIR3(cUnit, THUMB_ADD_RRR, reg2, reg2, reg3);
+    newLIR2(cUnit, THUMB_STMIA, reg2, (1<<reg0 | 1<<reg1));
 }
 
 /*
  * Load a field from an object instance
  *
  * Inst should be one of:
- *      ARMV5TE_LDR_RRR
- *      ARMV5TE_LDRB_RRR
- *      ARMV5TE_LDRH_RRR
- *      ARMV5TE_LDRSB_RRR
- *      ARMV5TE_LDRSH_RRR
+ *      THUMB_LDR_RRR
+ *      THUMB_LDRB_RRR
+ *      THUMB_LDRH_RRR
+ *      THUMB_LDRSB_RRR
+ *      THUMB_LDRSH_RRR
  */
-static void genIGet(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
+static void genIGet(CompilationUnit *cUnit, MIR *mir, ArmOpCode inst,
                     int fieldOffset)
 {
     DecodedInstruction *dInsn = &mir->dalvikInsn;
@@ -626,11 +626,11 @@ static void genIGet(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
  * Store a field to an object instance
  *
  * Inst should be one of:
- *      ARMV5TE_STR_RRR
- *      ARMV5TE_STRB_RRR
- *      ARMV5TE_STRH_RRR
+ *      THUMB_STR_RRR
+ *      THUMB_STRB_RRR
+ *      THUMB_STRH_RRR
  */
-static void genIPut(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
+static void genIPut(CompilationUnit *cUnit, MIR *mir, ArmOpCode inst,
                     int fieldOffset)
 {
     DecodedInstruction *dInsn = &mir->dalvikInsn;
@@ -656,13 +656,13 @@ static void genIPut(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
  * Generate array load
  *
  * Inst should be one of:
- *      ARMV5TE_LDR_RRR
- *      ARMV5TE_LDRB_RRR
- *      ARMV5TE_LDRH_RRR
- *      ARMV5TE_LDRSB_RRR
- *      ARMV5TE_LDRSH_RRR
+ *      THUMB_LDR_RRR
+ *      THUMB_LDRB_RRR
+ *      THUMB_LDRH_RRR
+ *      THUMB_LDRSB_RRR
+ *      THUMB_LDRSH_RRR
  */
-static void genArrayGet(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
+static void genArrayGet(CompilationUnit *cUnit, MIR *mir, ArmOpCode inst,
                         int vArray, int vIndex, int vDest, int scale)
 {
     int lenOffset = offsetof(ArrayObject, length);
@@ -678,17 +678,17 @@ static void genArrayGet(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
     loadValue(cUnit, vIndex, reg3);
 
     /* null object? */
-    Armv5teLIR * pcrLabel = genNullCheck(cUnit, vArray, reg2, mir->offset,
+    ArmLIR * pcrLabel = genNullCheck(cUnit, vArray, reg2, mir->offset,
                                          NULL);
-    newLIR3(cUnit, ARMV5TE_LDR_RRI5, reg0, reg2, lenOffset >> 2);  /* Get len */
-    newLIR2(cUnit, ARMV5TE_ADD_RI8, reg2, dataOffset); /* reg2 -> array data */
+    newLIR3(cUnit, THUMB_LDR_RRI5, reg0, reg2, lenOffset >> 2);  /* Get len */
+    newLIR2(cUnit, THUMB_ADD_RI8, reg2, dataOffset); /* reg2 -> array data */
     genBoundsCheck(cUnit, reg3, reg0, mir->offset, pcrLabel);
     if (scale) {
-        newLIR3(cUnit, ARMV5TE_LSL, reg3, reg3, scale);
+        newLIR3(cUnit, THUMB_LSL, reg3, reg3, scale);
     }
     if (scale==3) {
         newLIR3(cUnit, inst, reg0, reg2, reg3);
-        newLIR2(cUnit, ARMV5TE_ADD_RI8, reg2, 4);
+        newLIR2(cUnit, THUMB_ADD_RI8, reg2, 4);
         newLIR3(cUnit, inst, reg1, reg2, reg3);
         storeValuePair(cUnit, reg0, reg1, vDest, reg3);
     } else {
@@ -703,11 +703,11 @@ static void genArrayGet(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
  * Generate array store
  *
  * Inst should be one of:
- *      ARMV5TE_STR_RRR
- *      ARMV5TE_STRB_RRR
- *      ARMV5TE_STRH_RRR
+ *      THUMB_STR_RRR
+ *      THUMB_STRB_RRR
+ *      THUMB_STRH_RRR
  */
-static void genArrayPut(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
+static void genArrayPut(CompilationUnit *cUnit, MIR *mir, ArmOpCode inst,
                         int vArray, int vIndex, int vSrc, int scale)
 {
     int lenOffset = offsetof(ArrayObject, length);
@@ -723,10 +723,10 @@ static void genArrayPut(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
     loadValue(cUnit, vIndex, reg3);
 
     /* null object? */
-    Armv5teLIR * pcrLabel = genNullCheck(cUnit, vArray, reg2, mir->offset,
+    ArmLIR * pcrLabel = genNullCheck(cUnit, vArray, reg2, mir->offset,
                                          NULL);
-    newLIR3(cUnit, ARMV5TE_LDR_RRI5, reg0, reg2, lenOffset >> 2);  /* Get len */
-    newLIR2(cUnit, ARMV5TE_ADD_RI8, reg2, dataOffset); /* reg2 -> array data */
+    newLIR3(cUnit, THUMB_LDR_RRI5, reg0, reg2, lenOffset >> 2);  /* Get len */
+    newLIR2(cUnit, THUMB_ADD_RI8, reg2, dataOffset); /* reg2 -> array data */
     genBoundsCheck(cUnit, reg3, reg0, mir->offset, pcrLabel);
     /* at this point, reg2 points to array, reg3 is unscaled index */
     if (scale==3) {
@@ -737,7 +737,7 @@ static void genArrayPut(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
         updateLiveRegister(cUnit, vSrc, reg0);
     }
     if (scale) {
-        newLIR3(cUnit, ARMV5TE_LSL, reg3, reg3, scale);
+        newLIR3(cUnit, THUMB_LSL, reg3, reg3, scale);
     }
     /*
      * at this point, reg2 points to array, reg3 is scaled index, and
@@ -745,7 +745,7 @@ static void genArrayPut(CompilationUnit *cUnit, MIR *mir, Armv5teOpCode inst,
      */
     if (scale==3) {
         newLIR3(cUnit, inst, reg0, reg2, reg3);
-        newLIR2(cUnit, ARMV5TE_ADD_RI8, reg2, 4);
+        newLIR2(cUnit, THUMB_ADD_RI8, reg2, 4);
         newLIR3(cUnit, inst, reg1, reg2, reg3);
     } else {
         newLIR3(cUnit, inst, reg0, reg2, reg3);
@@ -824,7 +824,7 @@ bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
         case OP_NEG_FLOAT: {
             loadValue(cUnit, vSrc2, reg0);
             loadConstant(cUnit, reg1, 0x80000000);
-            newLIR3(cUnit, ARMV5TE_ADD_RRR, reg0, reg0, reg1);
+            newLIR3(cUnit, THUMB_ADD_RRR, reg0, reg0, reg1);
             storeValue(cUnit, reg0, vDest, reg1);
             return false;
         }
@@ -834,7 +834,7 @@ bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
     loadConstant(cUnit, r2, (int)funct);
     loadValue(cUnit, vSrc1, r0);
     loadValue(cUnit, vSrc2, r1);
-    newLIR1(cUnit, ARMV5TE_BLX_R, r2);
+    newLIR1(cUnit, THUMB_BLX_R, r2);
     storeValue(cUnit, r0, vDest, r1);
     return false;
 }
@@ -880,7 +880,7 @@ bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
         case OP_NEG_DOUBLE: {
             loadValuePair(cUnit, vSrc2, reg0, reg1);
             loadConstant(cUnit, reg2, 0x80000000);
-            newLIR3(cUnit, ARMV5TE_ADD_RRR, reg1, reg1, reg2);
+            newLIR3(cUnit, THUMB_ADD_RRR, reg1, reg1, reg2);
             storeValuePair(cUnit, reg0, reg1, vDest, reg2);
             return false;
         }
@@ -894,7 +894,7 @@ bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
     loadConstant(cUnit, r4PC, (int)funct);
     loadValuePair(cUnit, vSrc1, r0, r1);
     loadValuePair(cUnit, vSrc2, r2, r3);
-    newLIR1(cUnit, ARMV5TE_BLX_R, r4PC);
+    newLIR1(cUnit, THUMB_BLX_R, r4PC);
     storeValuePair(cUnit, r0, r1, vDest, r2);
     return false;
 }
@@ -902,8 +902,8 @@ bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
 static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir, int vDest,
                            int vSrc1, int vSrc2)
 {
-    int firstOp = ARMV5TE_BKPT;
-    int secondOp = ARMV5TE_BKPT;
+    int firstOp = THUMB_BKPT;
+    int secondOp = THUMB_BKPT;
     bool callOut = false;
     void *callTgt;
     int retReg = r0;
@@ -913,18 +913,18 @@ static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir, int vDest,
 
     switch (mir->dalvikInsn.opCode) {
         case OP_NOT_LONG:
-            firstOp = ARMV5TE_MVN;
-            secondOp = ARMV5TE_MVN;
+            firstOp = THUMB_MVN;
+            secondOp = THUMB_MVN;
             break;
         case OP_ADD_LONG:
         case OP_ADD_LONG_2ADDR:
-            firstOp = ARMV5TE_ADD_RRR;
-            secondOp = ARMV5TE_ADC;
+            firstOp = THUMB_ADD_RRR;
+            secondOp = THUMB_ADC;
             break;
         case OP_SUB_LONG:
         case OP_SUB_LONG_2ADDR:
-            firstOp = ARMV5TE_SUB_RRR;
-            secondOp = ARMV5TE_SBC;
+            firstOp = THUMB_SUB_RRR;
+            secondOp = THUMB_SBC;
             break;
         case OP_MUL_LONG:
         case OP_MUL_LONG_2ADDR:
@@ -949,18 +949,18 @@ static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir, int vDest,
             break;
         case OP_AND_LONG:
         case OP_AND_LONG_2ADDR:
-            firstOp = ARMV5TE_AND_RR;
-            secondOp = ARMV5TE_AND_RR;
+            firstOp = THUMB_AND_RR;
+            secondOp = THUMB_AND_RR;
             break;
         case OP_OR_LONG:
         case OP_OR_LONG_2ADDR:
-            firstOp = ARMV5TE_ORR;
-            secondOp = ARMV5TE_ORR;
+            firstOp = THUMB_ORR;
+            secondOp = THUMB_ORR;
             break;
         case OP_XOR_LONG:
         case OP_XOR_LONG_2ADDR:
-            firstOp = ARMV5TE_EOR;
-            secondOp = ARMV5TE_EOR;
+            firstOp = THUMB_EOR;
+            secondOp = THUMB_EOR;
             break;
         case OP_NEG_LONG: {
             reg0 = selectFirstRegister(cUnit, vSrc2, true);
@@ -970,8 +970,8 @@ static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir, int vDest,
 
             loadValuePair(cUnit, vSrc2, reg0, reg1);
             loadConstant(cUnit, reg3, 0);
-            newLIR3(cUnit, ARMV5TE_SUB_RRR, reg2, reg3, reg0);
-            newLIR2(cUnit, ARMV5TE_SBC, reg3, reg1);
+            newLIR3(cUnit, THUMB_SUB_RRR, reg2, reg3, reg0);
+            newLIR2(cUnit, THUMB_SBC, reg3, reg1);
             storeValuePair(cUnit, reg2, reg3, vDest, reg0);
             return false;
         }
@@ -996,7 +996,7 @@ static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir, int vDest,
         loadValuePair(cUnit, vSrc2, r2, r3);
         loadConstant(cUnit, r4PC, (int) callTgt);
         loadValuePair(cUnit, vSrc1, r0, r1);
-        newLIR1(cUnit, ARMV5TE_BLX_R, r4PC);
+        newLIR1(cUnit, THUMB_BLX_R, r4PC);
         storeValuePair(cUnit, retReg, retReg+1, vDest, r4PC);
     }
     return false;
@@ -1005,7 +1005,7 @@ static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir, int vDest,
 static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, int vDest,
                           int vSrc1, int vSrc2)
 {
-    int armOp = ARMV5TE_BKPT;
+    int armOp = THUMB_BKPT;
     bool callOut = false;
     bool checkZero = false;
     int retReg = r0;
@@ -1018,22 +1018,22 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, int vDest,
 
     switch (mir->dalvikInsn.opCode) {
         case OP_NEG_INT:
-            armOp = ARMV5TE_NEG;
+            armOp = THUMB_NEG;
             break;
         case OP_NOT_INT:
-            armOp = ARMV5TE_MVN;
+            armOp = THUMB_MVN;
             break;
         case OP_ADD_INT:
         case OP_ADD_INT_2ADDR:
-            armOp = ARMV5TE_ADD_RRR;
+            armOp = THUMB_ADD_RRR;
             break;
         case OP_SUB_INT:
         case OP_SUB_INT_2ADDR:
-            armOp = ARMV5TE_SUB_RRR;
+            armOp = THUMB_SUB_RRR;
             break;
         case OP_MUL_INT:
         case OP_MUL_INT_2ADDR:
-            armOp = ARMV5TE_MUL;
+            armOp = THUMB_MUL;
             break;
         case OP_DIV_INT:
         case OP_DIV_INT_2ADDR:
@@ -1052,27 +1052,27 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, int vDest,
             break;
         case OP_AND_INT:
         case OP_AND_INT_2ADDR:
-            armOp = ARMV5TE_AND_RR;
+            armOp = THUMB_AND_RR;
             break;
         case OP_OR_INT:
         case OP_OR_INT_2ADDR:
-            armOp = ARMV5TE_ORR;
+            armOp = THUMB_ORR;
             break;
         case OP_XOR_INT:
         case OP_XOR_INT_2ADDR:
-            armOp = ARMV5TE_EOR;
+            armOp = THUMB_EOR;
             break;
         case OP_SHL_INT:
         case OP_SHL_INT_2ADDR:
-            armOp = ARMV5TE_LSLV;
+            armOp = THUMB_LSLV;
             break;
         case OP_SHR_INT:
         case OP_SHR_INT_2ADDR:
-            armOp = ARMV5TE_ASRV;
+            armOp = THUMB_ASRV;
             break;
         case OP_USHR_INT:
         case OP_USHR_INT_2ADDR:
-            armOp = ARMV5TE_LSRV;
+            armOp = THUMB_LSRV;
             break;
         default:
             LOGE("Invalid word arith op: 0x%x(%d)",
@@ -1121,7 +1121,7 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, int vDest,
         if (checkZero) {
             genNullCheck(cUnit, vSrc2, r1, mir->offset, NULL);
         }
-        newLIR1(cUnit, ARMV5TE_BLX_R, r2);
+        newLIR1(cUnit, THUMB_BLX_R, r2);
         storeValue(cUnit, retReg, vDest, r2);
     }
     return false;
@@ -1180,7 +1180,7 @@ static bool genConversionCall(CompilationUnit *cUnit, MIR *mir, void *funct,
     } else {
         loadValuePair(cUnit, mir->dalvikInsn.vB, r0, r1);
     }
-    newLIR1(cUnit, ARMV5TE_BLX_R, r2);
+    newLIR1(cUnit, THUMB_BLX_R, r2);
     if (tgtSize == 1) {
         storeValue(cUnit, r0, mir->dalvikInsn.vA, r1);
     } else {
@@ -1198,7 +1198,7 @@ static bool genInlinedStringLength(CompilationUnit *cUnit, MIR *mir)
     loadValue(cUnit, dInsn->arg[0], regObj);
     genNullCheck(cUnit, dInsn->arg[0], regObj, mir->offset, NULL);
     loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_count, reg1);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, reg1, rGLUE, offset >> 2);
+    newLIR3(cUnit, THUMB_STR_RRI5, reg1, rGLUE, offset >> 2);
     return false;
 }
 
@@ -1223,18 +1223,18 @@ static bool genInlinedStringCharAt(CompilationUnit *cUnit, MIR *mir)
     int regOff = NEXT_REG(regMax);
     loadValue(cUnit, dInsn->arg[0], regObj);
     loadValue(cUnit, dInsn->arg[1], regIdx);
-    Armv5teLIR * pcrLabel = genNullCheck(cUnit, dInsn->arg[0], regObj,
+    ArmLIR * pcrLabel = genNullCheck(cUnit, dInsn->arg[0], regObj,
                                          mir->offset, NULL);
     loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_count, regMax);
     loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_offset, regOff);
     loadWordDisp(cUnit, regObj, gDvm.offJavaLangString_value, regObj);
     genBoundsCheck(cUnit, regIdx, regMax, mir->offset, pcrLabel);
 
-    newLIR2(cUnit, ARMV5TE_ADD_RI8, regObj, contents);
-    newLIR3(cUnit, ARMV5TE_ADD_RRR, regIdx, regIdx, regOff);
-    newLIR3(cUnit, ARMV5TE_ADD_RRR, regIdx, regIdx, regIdx);
-    newLIR3(cUnit, ARMV5TE_LDRH_RRR, regMax, regObj, regIdx);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, regMax, rGLUE, offset >> 2);
+    newLIR2(cUnit, THUMB_ADD_RI8, regObj, contents);
+    newLIR3(cUnit, THUMB_ADD_RRR, regIdx, regIdx, regOff);
+    newLIR3(cUnit, THUMB_ADD_RRR, regIdx, regIdx, regIdx);
+    newLIR3(cUnit, THUMB_LDRH_RRR, regMax, regObj, regIdx);
+    newLIR3(cUnit, THUMB_STR_RRI5, regMax, rGLUE, offset >> 2);
     return false;
 }
 
@@ -1246,10 +1246,10 @@ static bool genInlinedAbsInt(CompilationUnit *cUnit, MIR *mir)
     int sign = NEXT_REG(reg0);
     /* abs(x) = y<=x>>31, (x+y)^y.  Shorter in ARM/THUMB2, no skip in THUMB */
     loadValue(cUnit, dInsn->arg[0], reg0);
-    newLIR3(cUnit, ARMV5TE_ASR, sign, reg0, 31);
-    newLIR3(cUnit, ARMV5TE_ADD_RRR, reg0, reg0, sign);
-    newLIR2(cUnit, ARMV5TE_EOR, reg0, sign);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, reg0, rGLUE, offset >> 2);
+    newLIR3(cUnit, THUMB_ASR, sign, reg0, 31);
+    newLIR3(cUnit, THUMB_ADD_RRR, reg0, reg0, sign);
+    newLIR2(cUnit, THUMB_EOR, reg0, sign);
+    newLIR3(cUnit, THUMB_STR_RRI5, reg0, rGLUE, offset >> 2);
     return false;
 }
 
@@ -1261,8 +1261,8 @@ static bool genInlinedAbsFloat(CompilationUnit *cUnit, MIR *mir)
     int signMask = NEXT_REG(reg0);
     loadValue(cUnit, dInsn->arg[0], reg0);
     loadConstant(cUnit, signMask, 0x7fffffff);
-    newLIR2(cUnit, ARMV5TE_AND_RR, reg0, signMask);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, reg0, rGLUE, offset >> 2);
+    newLIR2(cUnit, THUMB_AND_RR, reg0, signMask);
+    newLIR3(cUnit, THUMB_STR_RRI5, reg0, rGLUE, offset >> 2);
     return false;
 }
 
@@ -1275,9 +1275,9 @@ static bool genInlinedAbsDouble(CompilationUnit *cUnit, MIR *mir)
     int signMask = NEXT_REG(ophi);
     loadValuePair(cUnit, dInsn->arg[0], oplo, ophi);
     loadConstant(cUnit, signMask, 0x7fffffff);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, oplo, rGLUE, offset >> 2);
-    newLIR2(cUnit, ARMV5TE_AND_RR, ophi, signMask);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, ophi, rGLUE, (offset >> 2)+1);
+    newLIR3(cUnit, THUMB_STR_RRI5, oplo, rGLUE, offset >> 2);
+    newLIR2(cUnit, THUMB_AND_RR, ophi, signMask);
+    newLIR3(cUnit, THUMB_STR_RRI5, ophi, rGLUE, (offset >> 2)+1);
     return false;
 }
 
@@ -1290,12 +1290,12 @@ static bool genInlinedMinMaxInt(CompilationUnit *cUnit, MIR *mir, bool isMin)
     int reg1 = NEXT_REG(reg0);
     loadValue(cUnit, dInsn->arg[0], reg0);
     loadValue(cUnit, dInsn->arg[1], reg1);
-    newLIR2(cUnit, ARMV5TE_CMP_RR, reg0, reg1);
-    Armv5teLIR *branch1 = newLIR2(cUnit, ARMV5TE_B_COND, 2,
+    newLIR2(cUnit, THUMB_CMP_RR, reg0, reg1);
+    ArmLIR *branch1 = newLIR2(cUnit, THUMB_B_COND, 2,
            isMin ? ARM_COND_LT : ARM_COND_GT);
-    newLIR2(cUnit, ARMV5TE_MOV_RR, reg0, reg1);
-    Armv5teLIR *target =
-        newLIR3(cUnit, ARMV5TE_STR_RRI5, reg0, rGLUE, offset >> 2);
+    newLIR2(cUnit, THUMB_MOV_RR, reg0, reg1);
+    ArmLIR *target =
+        newLIR3(cUnit, THUMB_STR_RRI5, reg0, rGLUE, offset >> 2);
     branch1->generic.target = (LIR *)target;
     return false;
 }
@@ -1309,19 +1309,19 @@ static bool genInlinedAbsLong(CompilationUnit *cUnit, MIR *mir)
     int sign = NEXT_REG(ophi);
     /* abs(x) = y<=x>>31, (x+y)^y.  Shorter in ARM/THUMB2, no skip in THUMB */
     loadValuePair(cUnit, dInsn->arg[0], oplo, ophi);
-    newLIR3(cUnit, ARMV5TE_ASR, sign, ophi, 31);
-    newLIR3(cUnit, ARMV5TE_ADD_RRR, oplo, oplo, sign);
-    newLIR2(cUnit, ARMV5TE_ADC, ophi, sign);
-    newLIR2(cUnit, ARMV5TE_EOR, oplo, sign);
-    newLIR2(cUnit, ARMV5TE_EOR, ophi, sign);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, oplo, rGLUE, offset >> 2);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, ophi, rGLUE, (offset >> 2)+1);
+    newLIR3(cUnit, THUMB_ASR, sign, ophi, 31);
+    newLIR3(cUnit, THUMB_ADD_RRR, oplo, oplo, sign);
+    newLIR2(cUnit, THUMB_ADC, ophi, sign);
+    newLIR2(cUnit, THUMB_EOR, oplo, sign);
+    newLIR2(cUnit, THUMB_EOR, ophi, sign);
+    newLIR3(cUnit, THUMB_STR_RRI5, oplo, rGLUE, offset >> 2);
+    newLIR3(cUnit, THUMB_STR_RRI5, ophi, rGLUE, (offset >> 2)+1);
     return false;
 }
 
 static void genProcessArgsNoRange(CompilationUnit *cUnit, MIR *mir,
                                   DecodedInstruction *dInsn,
-                                  Armv5teLIR **pcrLabel)
+                                  ArmLIR **pcrLabel)
 {
     unsigned int i;
     unsigned int regMask = 0;
@@ -1333,21 +1333,21 @@ static void genProcessArgsNoRange(CompilationUnit *cUnit, MIR *mir,
     }
     if (regMask) {
         /* Up to 5 args are pushed on top of FP - sizeofStackSaveArea */
-        newLIR2(cUnit, ARMV5TE_MOV_RR, r7, rFP);
-        newLIR2(cUnit, ARMV5TE_SUB_RI8, r7,
+        newLIR2(cUnit, THUMB_MOV_RR, r7, rFP);
+        newLIR2(cUnit, THUMB_SUB_RI8, r7,
                 sizeof(StackSaveArea) + (dInsn->vA << 2));
         /* generate null check */
         if (pcrLabel) {
             *pcrLabel = genNullCheck(cUnit, dInsn->arg[0], r0, mir->offset,
                                      NULL);
         }
-        newLIR2(cUnit, ARMV5TE_STMIA, r7, regMask);
+        newLIR2(cUnit, THUMB_STMIA, r7, regMask);
     }
 }
 
 static void genProcessArgsRange(CompilationUnit *cUnit, MIR *mir,
                                 DecodedInstruction *dInsn,
-                                Armv5teLIR **pcrLabel)
+                                ArmLIR **pcrLabel)
 {
     int srcOffset = dInsn->vC << 2;
     int numArgs = dInsn->vA;
@@ -1357,22 +1357,22 @@ static void genProcessArgsRange(CompilationUnit *cUnit, MIR *mir,
      * r7: &newFP[0]
      */
     if (srcOffset < 8) {
-        newLIR3(cUnit, ARMV5TE_ADD_RRI3, r4PC, rFP, srcOffset);
+        newLIR3(cUnit, THUMB_ADD_RRI3, r4PC, rFP, srcOffset);
     } else {
         loadConstant(cUnit, r4PC, srcOffset);
-        newLIR3(cUnit, ARMV5TE_ADD_RRR, r4PC, rFP, r4PC);
+        newLIR3(cUnit, THUMB_ADD_RRR, r4PC, rFP, r4PC);
     }
     /* load [r0 .. min(numArgs,4)] */
     regMask = (1 << ((numArgs < 4) ? numArgs : 4)) - 1;
-    newLIR2(cUnit, ARMV5TE_LDMIA, r4PC, regMask);
+    newLIR2(cUnit, THUMB_LDMIA, r4PC, regMask);
 
     if (sizeof(StackSaveArea) + (numArgs << 2) < 256) {
-        newLIR2(cUnit, ARMV5TE_MOV_RR, r7, rFP);
-        newLIR2(cUnit, ARMV5TE_SUB_RI8, r7,
+        newLIR2(cUnit, THUMB_MOV_RR, r7, rFP);
+        newLIR2(cUnit, THUMB_SUB_RI8, r7,
                 sizeof(StackSaveArea) + (numArgs << 2));
     } else {
         loadConstant(cUnit, r7, sizeof(StackSaveArea) + (numArgs << 2));
-        newLIR3(cUnit, ARMV5TE_SUB_RRR, r7, rFP, r7);
+        newLIR3(cUnit, THUMB_SUB_RRR, r7, rFP, r7);
     }
 
     /* generate null check */
@@ -1385,40 +1385,40 @@ static void genProcessArgsRange(CompilationUnit *cUnit, MIR *mir,
      * store previously loaded 4 values and load the next 4 values
      */
     if (numArgs >= 8) {
-        Armv5teLIR *loopLabel = NULL;
+        ArmLIR *loopLabel = NULL;
         /*
          * r0 contains "this" and it will be used later, so push it to the stack
          * first. Pushing r5 is just for stack alignment purposes.
          */
-        newLIR1(cUnit, ARMV5TE_PUSH, 1 << r0 | 1 << 5);
+        newLIR1(cUnit, THUMB_PUSH, 1 << r0 | 1 << 5);
         /* No need to generate the loop structure if numArgs <= 11 */
         if (numArgs > 11) {
             loadConstant(cUnit, 5, ((numArgs - 4) >> 2) << 2);
-            loopLabel = newLIR0(cUnit, ARMV5TE_PSEUDO_TARGET_LABEL);
+            loopLabel = newLIR0(cUnit, ARM_PSEUDO_TARGET_LABEL);
         }
-        newLIR2(cUnit, ARMV5TE_STMIA, r7, regMask);
-        newLIR2(cUnit, ARMV5TE_LDMIA, r4PC, regMask);
+        newLIR2(cUnit, THUMB_STMIA, r7, regMask);
+        newLIR2(cUnit, THUMB_LDMIA, r4PC, regMask);
         /* No need to generate the loop structure if numArgs <= 11 */
         if (numArgs > 11) {
-            newLIR2(cUnit, ARMV5TE_SUB_RI8, 5, 4);
+            newLIR2(cUnit, THUMB_SUB_RI8, 5, 4);
             genConditionalBranch(cUnit, ARM_COND_NE, loopLabel);
         }
     }
 
     /* Save the last batch of loaded values */
-    newLIR2(cUnit, ARMV5TE_STMIA, r7, regMask);
+    newLIR2(cUnit, THUMB_STMIA, r7, regMask);
 
     /* Generate the loop epilogue - don't use r0 */
     if ((numArgs > 4) && (numArgs % 4)) {
         regMask = ((1 << (numArgs & 0x3)) - 1) << 1;
-        newLIR2(cUnit, ARMV5TE_LDMIA, r4PC, regMask);
+        newLIR2(cUnit, THUMB_LDMIA, r4PC, regMask);
     }
     if (numArgs >= 8)
-        newLIR1(cUnit, ARMV5TE_POP, 1 << r0 | 1 << 5);
+        newLIR1(cUnit, THUMB_POP, 1 << r0 | 1 << 5);
 
     /* Save the modulo 4 arguments */
     if ((numArgs > 4) && (numArgs % 4)) {
-        newLIR2(cUnit, ARMV5TE_STMIA, r7, regMask);
+        newLIR2(cUnit, THUMB_STMIA, r7, regMask);
     }
 }
 
@@ -1427,14 +1427,14 @@ static void genProcessArgsRange(CompilationUnit *cUnit, MIR *mir,
  * is not a native method.
  */
 static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir,
-                                     BasicBlock *bb, Armv5teLIR *labelList,
-                                     Armv5teLIR *pcrLabel,
+                                     BasicBlock *bb, ArmLIR *labelList,
+                                     ArmLIR *pcrLabel,
                                      const Method *calleeMethod)
 {
-    Armv5teLIR *retChainingCell = &labelList[bb->fallThrough->id];
+    ArmLIR *retChainingCell = &labelList[bb->fallThrough->id];
 
     /* r1 = &retChainingCell */
-    Armv5teLIR *addrRetChain = newLIR3(cUnit, ARMV5TE_ADD_PC_REL,
+    ArmLIR *addrRetChain = newLIR3(cUnit, THUMB_ADD_PC_REL,
                                            r1, 0, 0);
     /* r4PC = dalvikCallsite */
     loadConstant(cUnit, r4PC,
@@ -1484,9 +1484,9 @@ static void genInvokeSingletonCommon(CompilationUnit *cUnit, MIR *mir,
  */
 static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
                                    int methodIndex,
-                                   Armv5teLIR *retChainingCell,
-                                   Armv5teLIR *predChainingCell,
-                                   Armv5teLIR *pcrLabel)
+                                   ArmLIR *retChainingCell,
+                                   ArmLIR *predChainingCell,
+                                   ArmLIR *pcrLabel)
 {
     /* "this" is already left in r0 by genProcessArgs* */
 
@@ -1495,13 +1495,13 @@ static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
                  (int) (cUnit->method->insns + mir->offset));
 
     /* r1 = &retChainingCell */
-    Armv5teLIR *addrRetChain = newLIR2(cUnit, ARMV5TE_ADD_PC_REL,
+    ArmLIR *addrRetChain = newLIR2(cUnit, THUMB_ADD_PC_REL,
                                        r1, 0);
     addrRetChain->generic.target = (LIR *) retChainingCell;
 
     /* r2 = &predictedChainingCell */
-    Armv5teLIR *predictedChainingCell =
-        newLIR2(cUnit, ARMV5TE_ADD_PC_REL, r2, 0);
+    ArmLIR *predictedChainingCell =
+        newLIR2(cUnit, THUMB_ADD_PC_REL, r2, 0);
     predictedChainingCell->generic.target = (LIR *) predChainingCell;
 
     genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN);
@@ -1515,8 +1515,8 @@ static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
      */
     if (pcrLabel == NULL) {
         int dPC = (int) (cUnit->method->insns + mir->offset);
-        pcrLabel = dvmCompilerNew(sizeof(Armv5teLIR), true);
-        pcrLabel->opCode = ARMV5TE_PSEUDO_PC_RECONSTRUCTION_CELL;
+        pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
+        pcrLabel->opCode = ARM_PSEUDO_PC_RECONSTRUCTION_CELL;
         pcrLabel->operands[0] = dPC;
         pcrLabel->operands[1] = mir->offset;
         /* Insert the place holder to the growable list */
@@ -1537,19 +1537,19 @@ static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
 
     /* r0 <- calleeMethod */
     if (methodIndex < 32) {
-        newLIR3(cUnit, ARMV5TE_LDR_RRI5, r0, r7, methodIndex);
+        newLIR3(cUnit, THUMB_LDR_RRI5, r0, r7, methodIndex);
     } else {
         loadConstant(cUnit, r0, methodIndex<<2);
-        newLIR3(cUnit, ARMV5TE_LDR_RRR, r0, r7, r0);
+        newLIR3(cUnit, THUMB_LDR_RRR, r0, r7, r0);
     }
 
     /* Check if rechain limit is reached */
-    newLIR2(cUnit, ARMV5TE_CMP_RI8, r1, 0);
+    newLIR2(cUnit, THUMB_CMP_RI8, r1, 0);
 
-    Armv5teLIR *bypassRechaining =
-        newLIR2(cUnit, ARMV5TE_B_COND, 0, ARM_COND_GT);
+    ArmLIR *bypassRechaining =
+        newLIR2(cUnit, THUMB_B_COND, 0, ARM_COND_GT);
 
-    newLIR3(cUnit, ARMV5TE_LDR_RRI5, r7, rGLUE,
+    newLIR3(cUnit, THUMB_LDR_RRI5, r7, rGLUE,
             offsetof(InterpState,
                      jitToInterpEntries.dvmJitToPatchPredictedChain)
             >> 2);
@@ -1563,10 +1563,10 @@ static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
      * when patching the chaining cell and will be clobbered upon
      * returning so it will be reconstructed again.
      */
-    newLIR1(cUnit, ARMV5TE_BLX_R, r7);
+    newLIR1(cUnit, THUMB_BLX_R, r7);
 
     /* r1 = &retChainingCell */
-    addrRetChain = newLIR3(cUnit, ARMV5TE_ADD_PC_REL, r1, 0, 0);
+    addrRetChain = newLIR3(cUnit, THUMB_ADD_PC_REL, r1, 0, 0);
     addrRetChain->generic.target = (LIR *) retChainingCell;
 
     bypassRechaining->generic.target = (LIR *) addrRetChain;
@@ -1592,21 +1592,21 @@ static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir,
  * The return LIR is a branch based on the comparison result. The actual branch
  * target will be setup in the caller.
  */
-static Armv5teLIR *genCheckPredictedChain(CompilationUnit *cUnit,
-                                          Armv5teLIR *predChainingCell,
-                                          Armv5teLIR *retChainingCell,
+static ArmLIR *genCheckPredictedChain(CompilationUnit *cUnit,
+                                          ArmLIR *predChainingCell,
+                                          ArmLIR *retChainingCell,
                                           MIR *mir)
 {
     /* r3 now contains this->clazz */
-    newLIR3(cUnit, ARMV5TE_LDR_RRI5, r3, r0,
+    newLIR3(cUnit, THUMB_LDR_RRI5, r3, r0,
             offsetof(Object, clazz) >> 2);
 
     /*
      * r2 now contains predicted class. The starting offset of the
      * cached value is 4 bytes into the chaining cell.
      */
-    Armv5teLIR *getPredictedClass =
-        newLIR3(cUnit, ARMV5TE_LDR_PC_REL, r2, 0,
+    ArmLIR *getPredictedClass =
+        newLIR3(cUnit, THUMB_LDR_PC_REL, r2, 0,
                 offsetof(PredictedChainingCell, clazz));
     getPredictedClass->generic.target = (LIR *) predChainingCell;
 
@@ -1614,14 +1614,14 @@ static Armv5teLIR *genCheckPredictedChain(CompilationUnit *cUnit,
      * r0 now contains predicted method. The starting offset of the
      * cached value is 8 bytes into the chaining cell.
      */
-    Armv5teLIR *getPredictedMethod =
-        newLIR3(cUnit, ARMV5TE_LDR_PC_REL, r0, 0,
+    ArmLIR *getPredictedMethod =
+        newLIR3(cUnit, THUMB_LDR_PC_REL, r0, 0,
                 offsetof(PredictedChainingCell, method));
     getPredictedMethod->generic.target = (LIR *) predChainingCell;
 
     /* Load the stats counter to see if it is time to unchain and refresh */
-    Armv5teLIR *getRechainingRequestCount =
-        newLIR3(cUnit, ARMV5TE_LDR_PC_REL, r7, 0,
+    ArmLIR *getRechainingRequestCount =
+        newLIR3(cUnit, THUMB_LDR_PC_REL, r7, 0,
                 offsetof(PredictedChainingCell, counter));
     getRechainingRequestCount->generic.target =
         (LIR *) predChainingCell;
@@ -1631,14 +1631,14 @@ static Armv5teLIR *genCheckPredictedChain(CompilationUnit *cUnit,
                  (int) (cUnit->method->insns + mir->offset));
 
     /* r1 = &retChainingCell */
-    Armv5teLIR *addrRetChain = newLIR3(cUnit, ARMV5TE_ADD_PC_REL,
+    ArmLIR *addrRetChain = newLIR3(cUnit, THUMB_ADD_PC_REL,
                                        r1, 0, 0);
     addrRetChain->generic.target = (LIR *) retChainingCell;
 
     /* Check if r2 (predicted class) == r3 (actual class) */
-    newLIR2(cUnit, ARMV5TE_CMP_RR, r2, r3);
+    newLIR2(cUnit, THUMB_CMP_RR, r2, r3);
 
-    return newLIR2(cUnit, ARMV5TE_B_COND, 0, ARM_COND_EQ);
+    return newLIR2(cUnit, THUMB_B_COND, 0, ARM_COND_EQ);
 }
 
 /* Geneate a branch to go back to the interpreter */
@@ -1646,9 +1646,9 @@ static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset)
 {
     /* r0 = dalvik pc */
     loadConstant(cUnit, r0, (int) (cUnit->method->insns + offset));
-    newLIR3(cUnit, ARMV5TE_LDR_RRI5, r1, rGLUE,
+    newLIR3(cUnit, THUMB_LDR_RRI5, r1, rGLUE,
             offsetof(InterpState, jitToInterpEntries.dvmJitToInterpPunt) >> 2);
-    newLIR1(cUnit, ARMV5TE_BLX_R, r1);
+    newLIR1(cUnit, THUMB_BLX_R, r1);
 }
 
 /*
@@ -1666,12 +1666,12 @@ static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir)
     }
     int entryAddr = offsetof(InterpState,
                              jitToInterpEntries.dvmJitToInterpSingleStep);
-    newLIR3(cUnit, ARMV5TE_LDR_RRI5, r2, rGLUE, entryAddr >> 2);
+    newLIR3(cUnit, THUMB_LDR_RRI5, r2, rGLUE, entryAddr >> 2);
     /* r0 = dalvik pc */
     loadConstant(cUnit, r0, (int) (cUnit->method->insns + mir->offset));
     /* r1 = dalvik pc of following instruction */
     loadConstant(cUnit, r1, (int) (cUnit->method->insns + mir->next->offset));
-    newLIR1(cUnit, ARMV5TE_BLX_R, r2);
+    newLIR1(cUnit, THUMB_BLX_R, r2);
 }
 
 
@@ -1683,7 +1683,7 @@ static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir)
  */
 
 static bool handleFmt10t_Fmt20t_Fmt30t(CompilationUnit *cUnit, MIR *mir,
-                                       BasicBlock *bb, Armv5teLIR *labelList)
+                                       BasicBlock *bb, ArmLIR *labelList)
 {
     /* For OP_GOTO, OP_GOTO_16, and OP_GOTO_32 */
     genUnconditionalBranch(cUnit, &labelList[bb->taken->id]);
@@ -1735,7 +1735,7 @@ static bool handleFmt11n_Fmt31i(CompilationUnit *cUnit, MIR *mir)
             reg1 = NEXT_REG(reg0);
             reg2 = NEXT_REG(reg1);
             loadConstant(cUnit, reg0, mir->dalvikInsn.vB);
-            newLIR3(cUnit, ARMV5TE_ASR, reg1, reg0, 31);
+            newLIR3(cUnit, THUMB_ASR, reg1, reg0, 31);
             storeValuePair(cUnit, reg0, reg1, mir->dalvikInsn.vA, reg2);
             break;
         }
@@ -1828,7 +1828,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
               (cUnit->method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]);
             assert(fieldPtr != NULL);
             loadConstant(cUnit, regvNone,  (int) fieldPtr + valOffset);
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, regvNone, regvNone, 0);
+            newLIR3(cUnit, THUMB_LDR_RRI5, regvNone, regvNone, 0);
             storeValue(cUnit, regvNone, mir->dalvikInsn.vA, NEXT_REG(regvNone));
             break;
         }
@@ -1843,7 +1843,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
             reg1 = NEXT_REG(reg0);
             reg2 = NEXT_REG(reg1);
             loadConstant(cUnit, reg2,  (int) fieldPtr + valOffset);
-            newLIR2(cUnit, ARMV5TE_LDMIA, reg2, (1<<reg0 | 1<<reg1));
+            newLIR2(cUnit, THUMB_LDMIA, reg2, (1<<reg0 | 1<<reg1));
             storeValuePair(cUnit, reg0, reg1, mir->dalvikInsn.vA, reg2);
             break;
         }
@@ -1861,7 +1861,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
             loadValue(cUnit, mir->dalvikInsn.vA, regvA);
             updateLiveRegister(cUnit, mir->dalvikInsn.vA, regvA);
             loadConstant(cUnit, NEXT_REG(regvA),  (int) fieldPtr + valOffset);
-            newLIR3(cUnit, ARMV5TE_STR_RRI5, regvA, NEXT_REG(regvA), 0);
+            newLIR3(cUnit, THUMB_STR_RRI5, regvA, NEXT_REG(regvA), 0);
             break;
         }
         case OP_SPUT_WIDE: {
@@ -1877,7 +1877,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
             loadValuePair(cUnit, mir->dalvikInsn.vA, reg0, reg1);
             updateLiveRegisterPair(cUnit, mir->dalvikInsn.vA, reg0, reg1);
             loadConstant(cUnit, reg2,  (int) fieldPtr + valOffset);
-            newLIR2(cUnit, ARMV5TE_STMIA, reg2, (1<<reg0 | 1<<reg1));
+            newLIR2(cUnit, THUMB_STMIA, reg2, (1<<reg0 | 1<<reg1));
             break;
         }
         case OP_NEW_INSTANCE: {
@@ -1898,7 +1898,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
             loadConstant(cUnit, r0, (int) classPtr);
             genExportPC(cUnit, mir, r2, r3 );
             loadConstant(cUnit, r1, ALLOC_DONT_TRACK);
-            newLIR1(cUnit, ARMV5TE_BLX_R, r4PC);
+            newLIR1(cUnit, THUMB_BLX_R, r4PC);
             /*
              * TODO: As coded, we'll bail and reinterpret on alloc failure.
              * Need a general mechanism to bail to thrown exception code.
@@ -1921,22 +1921,22 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir)
              * instruction made into a trace, but we are seeing NULL at runtime
              * so this check is temporarily used as a workaround.
              */
-            Armv5teLIR * pcrLabel = genZeroCheck(cUnit, r1, mir->offset, NULL);
-            newLIR2(cUnit, ARMV5TE_CMP_RI8, r0, 0);    /* Null? */
-            Armv5teLIR *branch1 =
-                newLIR2(cUnit, ARMV5TE_B_COND, 4, ARM_COND_EQ);
+            ArmLIR * pcrLabel = genZeroCheck(cUnit, r1, mir->offset, NULL);
+            newLIR2(cUnit, THUMB_CMP_RI8, r0, 0);    /* Null? */
+            ArmLIR *branch1 =
+                newLIR2(cUnit, THUMB_B_COND, 4, ARM_COND_EQ);
             /* r0 now contains object->clazz */
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r0, r0,
+            newLIR3(cUnit, THUMB_LDR_RRI5, r0, r0,
                     offsetof(Object, clazz) >> 2);
             loadConstant(cUnit, r4PC, (int)dvmInstanceofNonTrivial);
-            newLIR2(cUnit, ARMV5TE_CMP_RR, r0, r1);
-            Armv5teLIR *branch2 =
-                newLIR2(cUnit, ARMV5TE_B_COND, 2, ARM_COND_EQ);
-            newLIR1(cUnit, ARMV5TE_BLX_R, r4PC);
+            newLIR2(cUnit, THUMB_CMP_RR, r0, r1);
+            ArmLIR *branch2 =
+                newLIR2(cUnit, THUMB_B_COND, 2, ARM_COND_EQ);
+            newLIR1(cUnit, THUMB_BLX_R, r4PC);
             /* check cast failed - punt to the interpreter */
             genZeroCheck(cUnit, r0, mir->offset, pcrLabel);
             /* check cast passed - branch target here */
-            Armv5teLIR *target = newLIR0(cUnit, ARMV5TE_PSEUDO_TARGET_LABEL);
+            ArmLIR *target = newLIR0(cUnit, ARM_PSEUDO_TARGET_LABEL);
             branch1->generic.target = (LIR *)target;
             branch2->generic.target = (LIR *)target;
             break;
@@ -1954,30 +1954,30 @@ static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir)
         case OP_MOVE_EXCEPTION: {
             int offset = offsetof(InterpState, self);
             int exOffset = offsetof(Thread, exception);
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r1, rGLUE, offset >> 2);
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r0, r1, exOffset >> 2);
+            newLIR3(cUnit, THUMB_LDR_RRI5, r1, rGLUE, offset >> 2);
+            newLIR3(cUnit, THUMB_LDR_RRI5, r0, r1, exOffset >> 2);
             storeValue(cUnit, r0, mir->dalvikInsn.vA, r1);
            break;
         }
         case OP_MOVE_RESULT:
         case OP_MOVE_RESULT_OBJECT: {
             int offset = offsetof(InterpState, retval);
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r0, rGLUE, offset >> 2);
+            newLIR3(cUnit, THUMB_LDR_RRI5, r0, rGLUE, offset >> 2);
             storeValue(cUnit, r0, mir->dalvikInsn.vA, r1);
             break;
         }
         case OP_MOVE_RESULT_WIDE: {
             int offset = offsetof(InterpState, retval);
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r0, rGLUE, offset >> 2);
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r1, rGLUE, (offset >> 2)+1);
+            newLIR3(cUnit, THUMB_LDR_RRI5, r0, rGLUE, offset >> 2);
+            newLIR3(cUnit, THUMB_LDR_RRI5, r1, rGLUE, (offset >> 2)+1);
             storeValuePair(cUnit, r0, r1, mir->dalvikInsn.vA, r2);
             break;
         }
         case OP_RETURN_WIDE: {
             loadValuePair(cUnit, mir->dalvikInsn.vA, r0, r1);
             int offset = offsetof(InterpState, retval);
-            newLIR3(cUnit, ARMV5TE_STR_RRI5, r0, rGLUE, offset >> 2);
-            newLIR3(cUnit, ARMV5TE_STR_RRI5, r1, rGLUE, (offset >> 2)+1);
+            newLIR3(cUnit, THUMB_STR_RRI5, r0, rGLUE, offset >> 2);
+            newLIR3(cUnit, THUMB_STR_RRI5, r1, rGLUE, (offset >> 2)+1);
             genReturnCommon(cUnit,mir);
             break;
         }
@@ -1985,7 +1985,7 @@ static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir)
         case OP_RETURN_OBJECT: {
             loadValue(cUnit, mir->dalvikInsn.vA, r0);
             int offset = offsetof(InterpState, retval);
-            newLIR3(cUnit, ARMV5TE_STR_RRI5, r0, rGLUE, offset >> 2);
+            newLIR3(cUnit, THUMB_STR_RRI5, r0, rGLUE, offset >> 2);
             genReturnCommon(cUnit,mir);
             break;
         }
@@ -1999,7 +1999,7 @@ static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir)
         case OP_MONITOR_EXIT: {
             int offset = offsetof(InterpState, self);
             loadValue(cUnit, mir->dalvikInsn.vA, r1);
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r0, rGLUE, offset >> 2);
+            newLIR3(cUnit, THUMB_LDR_RRI5, r0, rGLUE, offset >> 2);
             if (dalvikOpCode == OP_MONITOR_ENTER) {
                 loadConstant(cUnit, r2, (int)dvmLockObject);
             } else {
@@ -2012,7 +2012,7 @@ static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir)
            */
             genNullCheck(cUnit, mir->dalvikInsn.vA, r1, mir->offset, NULL);
             /* Do the call */
-            newLIR1(cUnit, ARMV5TE_BLX_R, r2);
+            newLIR1(cUnit, THUMB_BLX_R, r2);
             break;
         }
         case OP_THROW: {
@@ -2123,7 +2123,7 @@ static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir)
             reg2 = NEXT_REG(reg1);
 
             loadValue(cUnit, vSrc2, reg0);
-            newLIR3(cUnit, ARMV5TE_ASR, reg1, reg0, 31);
+            newLIR3(cUnit, THUMB_ASR, reg1, reg0, 31);
             storeValuePair(cUnit, reg0, reg1, vSrc1Dest, reg2);
             break;
         }
@@ -2135,27 +2135,27 @@ static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir)
             break;
         case OP_INT_TO_BYTE:
             loadValue(cUnit, vSrc2, reg0);
-            newLIR3(cUnit, ARMV5TE_LSL, reg0, reg0, 24);
-            newLIR3(cUnit, ARMV5TE_ASR, reg0, reg0, 24);
+            newLIR3(cUnit, THUMB_LSL, reg0, reg0, 24);
+            newLIR3(cUnit, THUMB_ASR, reg0, reg0, 24);
             storeValue(cUnit, reg0, vSrc1Dest, reg1);
             break;
         case OP_INT_TO_SHORT:
             loadValue(cUnit, vSrc2, reg0);
-            newLIR3(cUnit, ARMV5TE_LSL, reg0, reg0, 16);
-            newLIR3(cUnit, ARMV5TE_ASR, reg0, reg0, 16);
+            newLIR3(cUnit, THUMB_LSL, reg0, reg0, 16);
+            newLIR3(cUnit, THUMB_ASR, reg0, reg0, 16);
             storeValue(cUnit, reg0, vSrc1Dest, reg1);
             break;
         case OP_INT_TO_CHAR:
             loadValue(cUnit, vSrc2, reg0);
-            newLIR3(cUnit, ARMV5TE_LSL, reg0, reg0, 16);
-            newLIR3(cUnit, ARMV5TE_LSR, reg0, reg0, 16);
+            newLIR3(cUnit, THUMB_LSL, reg0, reg0, 16);
+            newLIR3(cUnit, THUMB_LSR, reg0, reg0, 16);
             storeValue(cUnit, reg0, vSrc1Dest, reg1);
             break;
         case OP_ARRAY_LENGTH: {
             int lenOffset = offsetof(ArrayObject, length);
             loadValue(cUnit, vSrc2, reg0);
             genNullCheck(cUnit, vSrc2, reg0, mir->offset, NULL);
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, reg0, reg0, lenOffset >> 2);
+            newLIR3(cUnit, THUMB_LDR_RRI5, reg0, reg0, lenOffset >> 2);
             storeValue(cUnit, reg0, vSrc1Dest, reg1);
             break;
         }
@@ -2180,7 +2180,7 @@ static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir)
         reg2 = NEXT_REG(reg1);
 
         loadConstant(cUnit, reg0, BBBB);
-        newLIR3(cUnit, ARMV5TE_ASR, reg1, reg0, 31);
+        newLIR3(cUnit, THUMB_ASR, reg1, reg0, 31);
 
         /* Save the long values to the specified Dalvik register pair */
         storeValuePair(cUnit, reg0, reg1, vDest, reg2);
@@ -2201,14 +2201,14 @@ static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir)
 
 /* Compare agaist zero */
 static bool handleFmt21t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
-                         Armv5teLIR *labelList)
+                         ArmLIR *labelList)
 {
     OpCode dalvikOpCode = mir->dalvikInsn.opCode;
-    Armv5teConditionCode cond;
+    ArmConditionCode cond;
     int reg0 = selectFirstRegister(cUnit, mir->dalvikInsn.vA, false);
 
     loadValue(cUnit, mir->dalvikInsn.vA, reg0);
-    newLIR2(cUnit, ARMV5TE_CMP_RI8, reg0, 0);
+    newLIR2(cUnit, THUMB_CMP_RI8, reg0, 0);
 
     switch (dalvikOpCode) {
         case OP_IF_EQZ:
@@ -2262,22 +2262,22 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
         case OP_ADD_INT_LIT16:
             loadValue(cUnit, vSrc, reg0);
             if (lit <= 7 && lit >= 0) {
-                newLIR3(cUnit, ARMV5TE_ADD_RRI3, regDest, reg0, lit);
+                newLIR3(cUnit, THUMB_ADD_RRI3, regDest, reg0, lit);
                 storeValue(cUnit, regDest, vDest, reg1);
             } else if (lit <= 255 && lit >= 0) {
-                newLIR2(cUnit, ARMV5TE_ADD_RI8, reg0, lit);
+                newLIR2(cUnit, THUMB_ADD_RI8, reg0, lit);
                 storeValue(cUnit, reg0, vDest, reg1);
             } else if (lit >= -7 && lit <= 0) {
                 /* Convert to a small constant subtraction */
-                newLIR3(cUnit, ARMV5TE_SUB_RRI3, regDest, reg0, -lit);
+                newLIR3(cUnit, THUMB_SUB_RRI3, regDest, reg0, -lit);
                 storeValue(cUnit, regDest, vDest, reg1);
             } else if (lit >= -255 && lit <= 0) {
                 /* Convert to a small constant subtraction */
-                newLIR2(cUnit, ARMV5TE_SUB_RI8, reg0, -lit);
+                newLIR2(cUnit, THUMB_SUB_RI8, reg0, -lit);
                 storeValue(cUnit, reg0, vDest, reg1);
             } else {
                 loadConstant(cUnit, reg1, lit);
-                genBinaryOp(cUnit, vDest, ARMV5TE_ADD_RRR, reg0, reg1, regDest);
+                genBinaryOp(cUnit, vDest, THUMB_ADD_RRR, reg0, reg1, regDest);
             }
             break;
 
@@ -2285,7 +2285,7 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
         case OP_RSUB_INT:
             loadValue(cUnit, vSrc, reg1);
             loadConstant(cUnit, reg0, lit);
-            genBinaryOp(cUnit, vDest, ARMV5TE_SUB_RRR, reg0, reg1, regDest);
+            genBinaryOp(cUnit, vDest, THUMB_SUB_RRR, reg0, reg1, regDest);
             break;
 
         case OP_MUL_INT_LIT8:
@@ -2301,19 +2301,19 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
             switch (dalvikOpCode) {
                 case OP_MUL_INT_LIT8:
                 case OP_MUL_INT_LIT16:
-                    armOp = ARMV5TE_MUL;
+                    armOp = THUMB_MUL;
                     break;
                 case OP_AND_INT_LIT8:
                 case OP_AND_INT_LIT16:
-                    armOp = ARMV5TE_AND_RR;
+                    armOp = THUMB_AND_RR;
                     break;
                 case OP_OR_INT_LIT8:
                 case OP_OR_INT_LIT16:
-                    armOp = ARMV5TE_ORR;
+                    armOp = THUMB_ORR;
                     break;
                 case OP_XOR_INT_LIT8:
                 case OP_XOR_INT_LIT16:
-                    armOp = ARMV5TE_EOR;
+                    armOp = THUMB_EOR;
                     break;
                 default:
                     dvmAbort();
@@ -2327,13 +2327,13 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
             loadValue(cUnit, vSrc, reg0);
             switch (dalvikOpCode) {
                 case OP_SHL_INT_LIT8:
-                    armOp = ARMV5TE_LSL;
+                    armOp = THUMB_LSL;
                     break;
                 case OP_SHR_INT_LIT8:
-                    armOp = ARMV5TE_ASR;
+                    armOp = THUMB_ASR;
                     break;
                 case OP_USHR_INT_LIT8:
-                    armOp = ARMV5TE_LSR;
+                    armOp = THUMB_LSR;
                     break;
                 default: dvmAbort();
             }
@@ -2352,7 +2352,7 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
             loadConstant(cUnit, r2, (int)__aeabi_idiv);
             loadConstant(cUnit, r1, lit);
             loadValue(cUnit, vSrc, r0);
-            newLIR1(cUnit, ARMV5TE_BLX_R, r2);
+            newLIR1(cUnit, THUMB_BLX_R, r2);
             storeValue(cUnit, r0, vDest, r2);
             break;
 
@@ -2367,7 +2367,7 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir)
             loadConstant(cUnit, r2, (int)__aeabi_idivmod);
             loadConstant(cUnit, r1, lit);
             loadValue(cUnit, vSrc, r0);
-            newLIR1(cUnit, ARMV5TE_BLX_R, r2);
+            newLIR1(cUnit, THUMB_BLX_R, r2);
             storeValue(cUnit, r1, vDest, r2);
             break;
         default:
@@ -2404,11 +2404,11 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir)
             loadValue(cUnit, mir->dalvikInsn.vB, r1);  /* Len */
             loadConstant(cUnit, r0, (int) classPtr );
             loadConstant(cUnit, r4PC, (int)dvmAllocArrayByClass);
-            Armv5teLIR *pcrLabel =
+            ArmLIR *pcrLabel =
                 genRegImmCheck(cUnit, ARM_COND_MI, r1, 0, mir->offset, NULL);
             genExportPC(cUnit, mir, r2, r3 );
-            newLIR2(cUnit, ARMV5TE_MOV_IMM,r2,ALLOC_DONT_TRACK);
-            newLIR1(cUnit, ARMV5TE_BLX_R, r4PC);
+            newLIR2(cUnit, THUMB_MOV_IMM,r2,ALLOC_DONT_TRACK);
+            newLIR1(cUnit, THUMB_BLX_R, r4PC);
             /*
              * TODO: As coded, we'll bail and reinterpret on alloc failure.
              * Need a general mechanism to bail to thrown exception code.
@@ -2427,23 +2427,23 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir)
             assert(classPtr != NULL);
             loadValue(cUnit, mir->dalvikInsn.vB, r0);  /* Ref */
             loadConstant(cUnit, r2, (int) classPtr );
-            newLIR2(cUnit, ARMV5TE_CMP_RI8, r0, 0);    /* Null? */
+            newLIR2(cUnit, THUMB_CMP_RI8, r0, 0);    /* Null? */
             /* When taken r0 has NULL which can be used for store directly */
-            Armv5teLIR *branch1 = newLIR2(cUnit, ARMV5TE_B_COND, 4,
+            ArmLIR *branch1 = newLIR2(cUnit, THUMB_B_COND, 4,
                                           ARM_COND_EQ);
             /* r1 now contains object->clazz */
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r1, r0,
+            newLIR3(cUnit, THUMB_LDR_RRI5, r1, r0,
                     offsetof(Object, clazz) >> 2);
             loadConstant(cUnit, r4PC, (int)dvmInstanceofNonTrivial);
             loadConstant(cUnit, r0, 1);                /* Assume true */
-            newLIR2(cUnit, ARMV5TE_CMP_RR, r1, r2);
-            Armv5teLIR *branch2 = newLIR2(cUnit, ARMV5TE_B_COND, 2,
+            newLIR2(cUnit, THUMB_CMP_RR, r1, r2);
+            ArmLIR *branch2 = newLIR2(cUnit, THUMB_B_COND, 2,
                                           ARM_COND_EQ);
-            newLIR2(cUnit, ARMV5TE_MOV_RR, r0, r1);
-            newLIR2(cUnit, ARMV5TE_MOV_RR, r1, r2);
-            newLIR1(cUnit, ARMV5TE_BLX_R, r4PC);
+            newLIR2(cUnit, THUMB_MOV_RR, r0, r1);
+            newLIR2(cUnit, THUMB_MOV_RR, r1, r2);
+            newLIR1(cUnit, THUMB_BLX_R, r4PC);
             /* branch target here */
-            Armv5teLIR *target = newLIR0(cUnit, ARMV5TE_PSEUDO_TARGET_LABEL);
+            ArmLIR *target = newLIR0(cUnit, ARM_PSEUDO_TARGET_LABEL);
             storeValue(cUnit, r0, mir->dalvikInsn.vA, r1);
             branch1->generic.target = (LIR *)target;
             branch2->generic.target = (LIR *)target;
@@ -2454,34 +2454,34 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir)
             break;
         case OP_IGET:
         case OP_IGET_OBJECT:
-            genIGet(cUnit, mir, ARMV5TE_LDR_RRR, fieldOffset);
+            genIGet(cUnit, mir, THUMB_LDR_RRR, fieldOffset);
             break;
         case OP_IGET_BOOLEAN:
-            genIGet(cUnit, mir, ARMV5TE_LDRB_RRR, fieldOffset);
+            genIGet(cUnit, mir, THUMB_LDRB_RRR, fieldOffset);
             break;
         case OP_IGET_BYTE:
-            genIGet(cUnit, mir, ARMV5TE_LDRSB_RRR, fieldOffset);
+            genIGet(cUnit, mir, THUMB_LDRSB_RRR, fieldOffset);
             break;
         case OP_IGET_CHAR:
-            genIGet(cUnit, mir, ARMV5TE_LDRH_RRR, fieldOffset);
+            genIGet(cUnit, mir, THUMB_LDRH_RRR, fieldOffset);
             break;
         case OP_IGET_SHORT:
-            genIGet(cUnit, mir, ARMV5TE_LDRSH_RRR, fieldOffset);
+            genIGet(cUnit, mir, THUMB_LDRSH_RRR, fieldOffset);
             break;
         case OP_IPUT_WIDE:
             genIPutWide(cUnit, mir, fieldOffset);
             break;
         case OP_IPUT:
         case OP_IPUT_OBJECT:
-            genIPut(cUnit, mir, ARMV5TE_STR_RRR, fieldOffset);
+            genIPut(cUnit, mir, THUMB_STR_RRR, fieldOffset);
             break;
         case OP_IPUT_SHORT:
         case OP_IPUT_CHAR:
-            genIPut(cUnit, mir, ARMV5TE_STRH_RRR, fieldOffset);
+            genIPut(cUnit, mir, THUMB_STRH_RRR, fieldOffset);
             break;
         case OP_IPUT_BYTE:
         case OP_IPUT_BOOLEAN:
-            genIPut(cUnit, mir, ARMV5TE_STRB_RRR, fieldOffset);
+            genIPut(cUnit, mir, THUMB_STRB_RRR, fieldOffset);
             break;
         default:
             return true;
@@ -2496,11 +2496,11 @@ static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir)
     switch (dalvikOpCode) {
         case OP_IGET_QUICK:
         case OP_IGET_OBJECT_QUICK:
-            genIGet(cUnit, mir, ARMV5TE_LDR_RRR, fieldOffset);
+            genIGet(cUnit, mir, THUMB_LDR_RRR, fieldOffset);
             break;
         case OP_IPUT_QUICK:
         case OP_IPUT_OBJECT_QUICK:
-            genIPut(cUnit, mir, ARMV5TE_STR_RRR, fieldOffset);
+            genIPut(cUnit, mir, THUMB_STR_RRR, fieldOffset);
             break;
         case OP_IGET_WIDE_QUICK:
             genIGetWide(cUnit, mir, fieldOffset);
@@ -2517,10 +2517,10 @@ static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir)
 
 /* Compare agaist zero */
 static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
-                         Armv5teLIR *labelList)
+                         ArmLIR *labelList)
 {
     OpCode dalvikOpCode = mir->dalvikInsn.opCode;
-    Armv5teConditionCode cond;
+    ArmConditionCode cond;
     int reg0, reg1;
 
     if (cUnit->registerScoreboard.liveDalvikReg == (int) mir->dalvikInsn.vA) {
@@ -2536,7 +2536,7 @@ static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
         loadValue(cUnit, mir->dalvikInsn.vA, reg0);
         loadValue(cUnit, mir->dalvikInsn.vB, reg1);
     }
-    newLIR2(cUnit, ARMV5TE_CMP_RR, reg0, reg1);
+    newLIR2(cUnit, THUMB_CMP_RR, reg0, reg1);
 
     switch (dalvikOpCode) {
         case OP_IF_EQ:
@@ -2626,38 +2626,38 @@ static bool handleFmt23x(CompilationUnit *cUnit, MIR *mir)
             storeValue(cUnit, r0, vA, r1);
             break;
         case OP_AGET_WIDE:
-            genArrayGet(cUnit, mir, ARMV5TE_LDR_RRR, vB, vC, vA, 3);
+            genArrayGet(cUnit, mir, THUMB_LDR_RRR, vB, vC, vA, 3);
             break;
         case OP_AGET:
         case OP_AGET_OBJECT:
-            genArrayGet(cUnit, mir, ARMV5TE_LDR_RRR, vB, vC, vA, 2);
+            genArrayGet(cUnit, mir, THUMB_LDR_RRR, vB, vC, vA, 2);
             break;
         case OP_AGET_BOOLEAN:
-            genArrayGet(cUnit, mir, ARMV5TE_LDRB_RRR, vB, vC, vA, 0);
+            genArrayGet(cUnit, mir, THUMB_LDRB_RRR, vB, vC, vA, 0);
             break;
         case OP_AGET_BYTE:
-            genArrayGet(cUnit, mir, ARMV5TE_LDRSB_RRR, vB, vC, vA, 0);
+            genArrayGet(cUnit, mir, THUMB_LDRSB_RRR, vB, vC, vA, 0);
             break;
         case OP_AGET_CHAR:
-            genArrayGet(cUnit, mir, ARMV5TE_LDRH_RRR, vB, vC, vA, 1);
+            genArrayGet(cUnit, mir, THUMB_LDRH_RRR, vB, vC, vA, 1);
             break;
         case OP_AGET_SHORT:
-            genArrayGet(cUnit, mir, ARMV5TE_LDRSH_RRR, vB, vC, vA, 1);
+            genArrayGet(cUnit, mir, THUMB_LDRSH_RRR, vB, vC, vA, 1);
             break;
         case OP_APUT_WIDE:
-            genArrayPut(cUnit, mir, ARMV5TE_STR_RRR, vB, vC, vA, 3);
+            genArrayPut(cUnit, mir, THUMB_STR_RRR, vB, vC, vA, 3);
             break;
         case OP_APUT:
         case OP_APUT_OBJECT:
-            genArrayPut(cUnit, mir, ARMV5TE_STR_RRR, vB, vC, vA, 2);
+            genArrayPut(cUnit, mir, THUMB_STR_RRR, vB, vC, vA, 2);
             break;
         case OP_APUT_SHORT:
         case OP_APUT_CHAR:
-            genArrayPut(cUnit, mir, ARMV5TE_STRH_RRR, vB, vC, vA, 1);
+            genArrayPut(cUnit, mir, THUMB_STRH_RRR, vB, vC, vA, 1);
             break;
         case OP_APUT_BYTE:
         case OP_APUT_BOOLEAN:
-            genArrayPut(cUnit, mir, ARMV5TE_STRB_RRR, vB, vC, vA, 0);
+            genArrayPut(cUnit, mir, THUMB_STRB_RRR, vB, vC, vA, 0);
             break;
         default:
             return true;
@@ -2675,7 +2675,7 @@ static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir)
             loadConstant(cUnit, r1, (mir->dalvikInsn.vB << 1) +
                  (int) (cUnit->method->insns + mir->offset));
             genExportPC(cUnit, mir, r2, r3 );
-            newLIR1(cUnit, ARMV5TE_BLX_R, r4PC);
+            newLIR1(cUnit, THUMB_BLX_R, r4PC);
             genZeroCheck(cUnit, r0, mir->offset, NULL);
             break;
         }
@@ -2695,14 +2695,14 @@ static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir)
             loadValue(cUnit, mir->dalvikInsn.vA, r1);
             loadConstant(cUnit, r0, (mir->dalvikInsn.vB << 1) +
                  (int) (cUnit->method->insns + mir->offset));
-            newLIR1(cUnit, ARMV5TE_BLX_R, r4PC);
+            newLIR1(cUnit, THUMB_BLX_R, r4PC);
             loadConstant(cUnit, r1, (int)(cUnit->method->insns + mir->offset));
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r2, rGLUE,
+            newLIR3(cUnit, THUMB_LDR_RRI5, r2, rGLUE,
                 offsetof(InterpState, jitToInterpEntries.dvmJitToInterpNoChain)
                     >> 2);
-            newLIR3(cUnit, ARMV5TE_ADD_RRR, r0, r0, r0);
-            newLIR3(cUnit, ARMV5TE_ADD_RRR, r4PC, r0, r1);
-            newLIR1(cUnit, ARMV5TE_BLX_R, r2);
+            newLIR3(cUnit, THUMB_ADD_RRR, r0, r0, r0);
+            newLIR3(cUnit, THUMB_ADD_RRR, r4PC, r0, r1);
+            newLIR1(cUnit, THUMB_BLX_R, r2);
             break;
         }
         default:
@@ -2712,10 +2712,10 @@ static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir)
 }
 
 static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
-                             Armv5teLIR *labelList)
+                             ArmLIR *labelList)
 {
-    Armv5teLIR *retChainingCell = &labelList[bb->fallThrough->id];
-    Armv5teLIR *pcrLabel = NULL;
+    ArmLIR *retChainingCell = &labelList[bb->fallThrough->id];
+    ArmLIR *pcrLabel = NULL;
 
     DecodedInstruction *dInsn = &mir->dalvikInsn;
     switch (mir->dalvikInsn.opCode) {
@@ -2726,7 +2726,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
          */
         case OP_INVOKE_VIRTUAL:
         case OP_INVOKE_VIRTUAL_RANGE: {
-            Armv5teLIR *predChainingCell = &labelList[bb->taken->id];
+            ArmLIR *predChainingCell = &labelList[bb->taken->id];
             int methodIndex =
                 cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]->
                 methodIndex;
@@ -2870,7 +2870,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
          */
         case OP_INVOKE_INTERFACE:
         case OP_INVOKE_INTERFACE_RANGE: {
-            Armv5teLIR *predChainingCell = &labelList[bb->taken->id];
+            ArmLIR *predChainingCell = &labelList[bb->taken->id];
             int methodIndex = dInsn->vB;
 
             if (mir->dalvikInsn.opCode == OP_INVOKE_INTERFACE)
@@ -2885,13 +2885,13 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
                          (int) (cUnit->method->insns + mir->offset));
 
             /* r1 = &retChainingCell */
-            Armv5teLIR *addrRetChain = newLIR2(cUnit, ARMV5TE_ADD_PC_REL,
+            ArmLIR *addrRetChain = newLIR2(cUnit, THUMB_ADD_PC_REL,
                                                r1, 0);
             addrRetChain->generic.target = (LIR *) retChainingCell;
 
             /* r2 = &predictedChainingCell */
-            Armv5teLIR *predictedChainingCell =
-                newLIR2(cUnit, ARMV5TE_ADD_PC_REL, r2, 0);
+            ArmLIR *predictedChainingCell =
+                newLIR2(cUnit, THUMB_ADD_PC_REL, r2, 0);
             predictedChainingCell->generic.target = (LIR *) predChainingCell;
 
             genDispatchToHandler(cUnit, TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN);
@@ -2905,8 +2905,8 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
              */
             if (pcrLabel == NULL) {
                 int dPC = (int) (cUnit->method->insns + mir->offset);
-                pcrLabel = dvmCompilerNew(sizeof(Armv5teLIR), true);
-                pcrLabel->opCode = ARMV5TE_PSEUDO_PC_RECONSTRUCTION_CELL;
+                pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true);
+                pcrLabel->opCode = ARM_PSEUDO_PC_RECONSTRUCTION_CELL;
                 pcrLabel->operands[0] = dPC;
                 pcrLabel->operands[1] = mir->offset;
                 /* Insert the place holder to the growable list */
@@ -2926,12 +2926,12 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
              */
 
             /* Save count, &predictedChainCell, and class to high regs first */
-            newLIR2(cUnit, ARMV5TE_MOV_RR_L2H, r9 & THUMB_REG_MASK, r1);
-            newLIR2(cUnit, ARMV5TE_MOV_RR_L2H, r10 & THUMB_REG_MASK, r2);
-            newLIR2(cUnit, ARMV5TE_MOV_RR_L2H, r12 & THUMB_REG_MASK, r3);
+            newLIR2(cUnit, THUMB_MOV_RR_L2H, r9 & THUMB_REG_MASK, r1);
+            newLIR2(cUnit, THUMB_MOV_RR_L2H, r10 & THUMB_REG_MASK, r2);
+            newLIR2(cUnit, THUMB_MOV_RR_L2H, r12 & THUMB_REG_MASK, r3);
 
             /* r0 now contains this->clazz */
-            newLIR2(cUnit, ARMV5TE_MOV_RR, r0, r3);
+            newLIR2(cUnit, THUMB_MOV_RR, r0, r3);
 
             /* r1 = BBBB */
             loadConstant(cUnit, r1, dInsn->vB);
@@ -2944,25 +2944,25 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
 
             loadConstant(cUnit, r7,
                          (intptr_t) dvmFindInterfaceMethodInCache);
-            newLIR1(cUnit, ARMV5TE_BLX_R, r7);
+            newLIR1(cUnit, THUMB_BLX_R, r7);
 
             /* r0 = calleeMethod (returned from dvmFindInterfaceMethodInCache */
 
-            newLIR2(cUnit, ARMV5TE_MOV_RR_H2L, r1, r9 & THUMB_REG_MASK);
+            newLIR2(cUnit, THUMB_MOV_RR_H2L, r1, r9 & THUMB_REG_MASK);
 
             /* Check if rechain limit is reached */
-            newLIR2(cUnit, ARMV5TE_CMP_RI8, r1, 0);
+            newLIR2(cUnit, THUMB_CMP_RI8, r1, 0);
 
-            Armv5teLIR *bypassRechaining =
-                newLIR2(cUnit, ARMV5TE_B_COND, 0, ARM_COND_GT);
+            ArmLIR *bypassRechaining =
+                newLIR2(cUnit, THUMB_B_COND, 0, ARM_COND_GT);
 
-            newLIR3(cUnit, ARMV5TE_LDR_RRI5, r7, rGLUE,
+            newLIR3(cUnit, THUMB_LDR_RRI5, r7, rGLUE,
                     offsetof(InterpState,
                              jitToInterpEntries.dvmJitToPatchPredictedChain)
                     >> 2);
 
-            newLIR2(cUnit, ARMV5TE_MOV_RR_H2L, r2, r10 & THUMB_REG_MASK);
-            newLIR2(cUnit, ARMV5TE_MOV_RR_H2L, r3, r12 & THUMB_REG_MASK);
+            newLIR2(cUnit, THUMB_MOV_RR_H2L, r2, r10 & THUMB_REG_MASK);
+            newLIR2(cUnit, THUMB_MOV_RR_H2L, r3, r12 & THUMB_REG_MASK);
 
             /*
              * r0 = calleeMethod
@@ -2973,10 +2973,10 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
              * when patching the chaining cell and will be clobbered upon
              * returning so it will be reconstructed again.
              */
-            newLIR1(cUnit, ARMV5TE_BLX_R, r7);
+            newLIR1(cUnit, THUMB_BLX_R, r7);
 
             /* r1 = &retChainingCell */
-            addrRetChain = newLIR3(cUnit, ARMV5TE_ADD_PC_REL,
+            addrRetChain = newLIR3(cUnit, THUMB_ADD_PC_REL,
                                                r1, 0, 0);
             addrRetChain->generic.target = (LIR *) retChainingCell;
 
@@ -3012,11 +3012,11 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb,
 }
 
 static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir,
-                               BasicBlock *bb, Armv5teLIR *labelList)
+                               BasicBlock *bb, ArmLIR *labelList)
 {
-    Armv5teLIR *retChainingCell = &labelList[bb->fallThrough->id];
-    Armv5teLIR *predChainingCell = &labelList[bb->taken->id];
-    Armv5teLIR *pcrLabel = NULL;
+    ArmLIR *retChainingCell = &labelList[bb->fallThrough->id];
+    ArmLIR *predChainingCell = &labelList[bb->taken->id];
+    ArmLIR *pcrLabel = NULL;
 
     DecodedInstruction *dInsn = &mir->dalvikInsn;
     switch (mir->dalvikInsn.opCode) {
@@ -3119,10 +3119,10 @@ static bool handleFmt3inline(CompilationUnit *cUnit, MIR *mir)
             }
 
             /* Materialize pointer to retval & push */
-            newLIR2(cUnit, ARMV5TE_MOV_RR, r4PC, rGLUE);
-            newLIR2(cUnit, ARMV5TE_ADD_RI8, r4PC, offset);
+            newLIR2(cUnit, THUMB_MOV_RR, r4PC, rGLUE);
+            newLIR2(cUnit, THUMB_ADD_RI8, r4PC, offset);
             /* Push r4 and (just to take up space) r5) */
-            newLIR1(cUnit, ARMV5TE_PUSH, (1<<r4PC | 1<<rFP));
+            newLIR1(cUnit, THUMB_PUSH, (1<<r4PC | 1<<rFP));
 
             /* Get code pointer to inline routine */
             loadConstant(cUnit, r4PC, (int)inLineTable[operation].func);
@@ -3135,10 +3135,10 @@ static bool handleFmt3inline(CompilationUnit *cUnit, MIR *mir)
                 loadValue(cUnit, dInsn->arg[i], i);
             }
             /* Call inline routine */
-            newLIR1(cUnit, ARMV5TE_BLX_R, r4PC);
+            newLIR1(cUnit, THUMB_BLX_R, r4PC);
 
             /* Strip frame */
-            newLIR1(cUnit, ARMV5TE_ADD_SPI7, 2);
+            newLIR1(cUnit, THUMB_ADD_SPI7, 2);
 
             /* Did we throw? If so, redo under interpreter*/
             genZeroCheck(cUnit, r0, mir->offset, NULL);
@@ -3171,9 +3171,9 @@ static bool handleFmt51l(CompilationUnit *cUnit, MIR *mir)
 static void handleNormalChainingCell(CompilationUnit *cUnit,
                                      unsigned int offset)
 {
-    newLIR3(cUnit, ARMV5TE_LDR_RRI5, r0, rGLUE,
+    newLIR3(cUnit, THUMB_LDR_RRI5, r0, rGLUE,
         offsetof(InterpState, jitToInterpEntries.dvmJitToInterpNormal) >> 2);
-    newLIR1(cUnit, ARMV5TE_BLX_R, r0);
+    newLIR1(cUnit, THUMB_BLX_R, r0);
     addWordData(cUnit, (int) (cUnit->method->insns + offset), true);
 }
 
@@ -3184,9 +3184,9 @@ static void handleNormalChainingCell(CompilationUnit *cUnit,
 static void handleHotChainingCell(CompilationUnit *cUnit,
                                   unsigned int offset)
 {
-    newLIR3(cUnit, ARMV5TE_LDR_RRI5, r0, rGLUE,
+    newLIR3(cUnit, THUMB_LDR_RRI5, r0, rGLUE,
         offsetof(InterpState, jitToInterpEntries.dvmJitToTraceSelect) >> 2);
-    newLIR1(cUnit, ARMV5TE_BLX_R, r0);
+    newLIR1(cUnit, THUMB_BLX_R, r0);
     addWordData(cUnit, (int) (cUnit->method->insns + offset), true);
 }
 
@@ -3194,9 +3194,9 @@ static void handleHotChainingCell(CompilationUnit *cUnit,
 static void handleInvokeSingletonChainingCell(CompilationUnit *cUnit,
                                               const Method *callee)
 {
-    newLIR3(cUnit, ARMV5TE_LDR_RRI5, r0, rGLUE,
+    newLIR3(cUnit, THUMB_LDR_RRI5, r0, rGLUE,
         offsetof(InterpState, jitToInterpEntries.dvmJitToTraceSelect) >> 2);
-    newLIR1(cUnit, ARMV5TE_BLX_R, r0);
+    newLIR1(cUnit, THUMB_BLX_R, r0);
     addWordData(cUnit, (int) (callee->insns), true);
 }
 
@@ -3219,10 +3219,10 @@ static void handleInvokePredictedChainingCell(CompilationUnit *cUnit)
 
 /* Load the Dalvik PC into r0 and jump to the specified target */
 static void handlePCReconstruction(CompilationUnit *cUnit,
-                                   Armv5teLIR *targetLabel)
+                                   ArmLIR *targetLabel)
 {
-    Armv5teLIR **pcrLabel =
-        (Armv5teLIR **) cUnit->pcReconstructionList.elemList;
+    ArmLIR **pcrLabel =
+        (ArmLIR **) cUnit->pcReconstructionList.elemList;
     int numElems = cUnit->pcReconstructionList.numUsed;
     int i;
     for (i = 0; i < numElems; i++) {
@@ -3237,8 +3237,8 @@ static void handlePCReconstruction(CompilationUnit *cUnit,
 void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
 {
     /* Used to hold the labels of each block */
-    Armv5teLIR *labelList =
-        dvmCompilerNew(sizeof(Armv5teLIR) * cUnit->numBlocks, true);
+    ArmLIR *labelList =
+        dvmCompilerNew(sizeof(ArmLIR) * cUnit->numBlocks, true);
     GrowableList chainingListByType[CHAINING_CELL_LAST];
     int i;
 
@@ -3267,20 +3267,20 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
          *       add   r1, #1
          *       str   r1, [r0]
          */
-        newLIR1(cUnit, ARMV5TE_16BIT_DATA, 0);
-        newLIR1(cUnit, ARMV5TE_16BIT_DATA, 0);
+        newLIR1(cUnit, ARM_16BIT_DATA, 0);
+        newLIR1(cUnit, ARM_16BIT_DATA, 0);
         cUnit->chainCellOffsetLIR =
-            (LIR *) newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
+            (LIR *) newLIR1(cUnit, ARM_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
         cUnit->headerSize = 6;
-        newLIR2(cUnit, ARMV5TE_MOV_RR_H2L, r0, rpc & THUMB_REG_MASK);
-        newLIR2(cUnit, ARMV5TE_SUB_RI8, r0, 10);
-        newLIR3(cUnit, ARMV5TE_LDR_RRI5, r1, r0, 0);
-        newLIR2(cUnit, ARMV5TE_ADD_RI8, r1, 1);
-        newLIR3(cUnit, ARMV5TE_STR_RRI5, r1, r0, 0);
+        newLIR2(cUnit, THUMB_MOV_RR_H2L, r0, rpc & THUMB_REG_MASK);
+        newLIR2(cUnit, THUMB_SUB_RI8, r0, 10);
+        newLIR3(cUnit, THUMB_LDR_RRI5, r1, r0, 0);
+        newLIR2(cUnit, THUMB_ADD_RI8, r1, 1);
+        newLIR3(cUnit, THUMB_STR_RRI5, r1, r0, 0);
     } else {
          /* Just reserve 2 bytes for the chain cell offset */
         cUnit->chainCellOffsetLIR =
-            (LIR *) newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
+            (LIR *) newLIR1(cUnit, ARM_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
         cUnit->headerSize = 2;
     }
 
@@ -3300,20 +3300,20 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
         }
 
         if (blockList[i]->blockType == DALVIK_BYTECODE) {
-            labelList[i].opCode = ARMV5TE_PSEUDO_NORMAL_BLOCK_LABEL;
+            labelList[i].opCode = ARM_PSEUDO_NORMAL_BLOCK_LABEL;
             /* Reset the register state */
             resetRegisterScoreboard(cUnit);
         } else {
             switch (blockList[i]->blockType) {
                 case CHAINING_CELL_NORMAL:
-                    labelList[i].opCode = ARMV5TE_PSEUDO_CHAINING_CELL_NORMAL;
+                    labelList[i].opCode = ARM_PSEUDO_CHAINING_CELL_NORMAL;
                     /* handle the codegen later */
                     dvmInsertGrowableList(
                         &chainingListByType[CHAINING_CELL_NORMAL], (void *) i);
                     break;
                 case CHAINING_CELL_INVOKE_SINGLETON:
                     labelList[i].opCode =
-                        ARMV5TE_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON;
+                        ARM_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON;
                     labelList[i].operands[0] =
                         (int) blockList[i]->containingMethod;
                     /* handle the codegen later */
@@ -3323,7 +3323,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
                     break;
                 case CHAINING_CELL_INVOKE_PREDICTED:
                     labelList[i].opCode =
-                        ARMV5TE_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED;
+                        ARM_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED;
                     /* handle the codegen later */
                     dvmInsertGrowableList(
                         &chainingListByType[CHAINING_CELL_INVOKE_PREDICTED],
@@ -3331,7 +3331,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
                     break;
                 case CHAINING_CELL_HOT:
                     labelList[i].opCode =
-                        ARMV5TE_PSEUDO_CHAINING_CELL_HOT;
+                        ARM_PSEUDO_CHAINING_CELL_HOT;
                     /* handle the codegen later */
                     dvmInsertGrowableList(
                         &chainingListByType[CHAINING_CELL_HOT],
@@ -3340,18 +3340,18 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
                 case PC_RECONSTRUCTION:
                     /* Make sure exception handling block is next */
                     labelList[i].opCode =
-                        ARMV5TE_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL;
+                        ARM_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL;
                     assert (i == cUnit->numBlocks - 2);
                     handlePCReconstruction(cUnit, &labelList[i+1]);
                     break;
                 case EXCEPTION_HANDLING:
-                    labelList[i].opCode = ARMV5TE_PSEUDO_EH_BLOCK_LABEL;
+                    labelList[i].opCode = ARM_PSEUDO_EH_BLOCK_LABEL;
                     if (cUnit->pcReconstructionList.numUsed) {
-                        newLIR3(cUnit, ARMV5TE_LDR_RRI5, r1, rGLUE,
+                        newLIR3(cUnit, THUMB_LDR_RRI5, r1, rGLUE,
                             offsetof(InterpState,
                                      jitToInterpEntries.dvmJitToInterpPunt)
                             >> 2);
-                        newLIR1(cUnit, ARMV5TE_BLX_R, r1);
+                        newLIR1(cUnit, THUMB_BLX_R, r1);
                     }
                     break;
                 default:
@@ -3360,14 +3360,14 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
             continue;
         }
 
-        Armv5teLIR *headLIR = NULL;
+        ArmLIR *headLIR = NULL;
 
         for (mir = blockList[i]->firstMIRInsn; mir; mir = mir->next) {
             OpCode dalvikOpCode = mir->dalvikInsn.opCode;
             InstructionFormat dalvikFormat =
                 dexGetInstrFormat(gDvm.instrFormat, dalvikOpCode);
-            Armv5teLIR *boundaryLIR =
-                newLIR2(cUnit, ARMV5TE_PSEUDO_DALVIK_BYTECODE_BOUNDARY,
+            ArmLIR *boundaryLIR =
+                newLIR2(cUnit, ARM_PSEUDO_DALVIK_BYTECODE_BOUNDARY,
                         mir->offset,dalvikOpCode);
             /* Remember the first LIR for this block */
             if (headLIR == NULL) {
@@ -3511,7 +3511,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
             int blockId = blockIdList[j];
 
             /* Align this chaining cell first */
-            newLIR0(cUnit, ARMV5TE_PSEUDO_ALIGN4);
+            newLIR0(cUnit, ARM_PSEUDO_ALIGN4);
 
             /* Insert the pseudo chaining instruction */
             dvmCompilerAppendLIR(cUnit, (LIR *) &labelList[blockId]);

diff --git a/vm/compiler/codegen/armv5te/GlobalOptimizations.c b/vm/compiler/codegen/arm/GlobalOptimizations.c
similarity index 80%
rename from vm/compiler/codegen/armv5te/GlobalOptimizations.c
rename to vm/compiler/codegen/arm/GlobalOptimizations.c
index 2b8ec6f..40e1f07 100644 (file)
--- a/vm/compiler/codegen/armv5te/GlobalOptimizations.c
+++ b/vm/compiler/codegen/arm/GlobalOptimizations.c
@@ -16,7 +16,7 @@
 
 #include "Dalvik.h"
 #include "vm/compiler/CompilerInternals.h"
-#include "Armv5teLIR.h"
+#include "ArmLIR.h"
 
 /*
  * Identify unconditional branches that jump to the immediate successor of the
@@ -24,15 +24,15 @@
  */
 static void applyRedundantBranchElimination(CompilationUnit *cUnit)
 {
-    Armv5teLIR *thisLIR;
+    ArmLIR *thisLIR;
 
-    for (thisLIR = (Armv5teLIR *) cUnit->firstLIRInsn;
-         thisLIR != (Armv5teLIR *) cUnit->lastLIRInsn;
+    for (thisLIR = (ArmLIR *) cUnit->firstLIRInsn;
+         thisLIR != (ArmLIR *) cUnit->lastLIRInsn;
          thisLIR = NEXT_LIR(thisLIR)) {
 
         /* Branch to the next instruction */
-        if (thisLIR->opCode == ARMV5TE_B_UNCOND) {
-            Armv5teLIR *nextLIR = thisLIR;
+        if (thisLIR->opCode == THUMB_B_UNCOND) {
+            ArmLIR *nextLIR = thisLIR;
 
             while (true) {
                 nextLIR = NEXT_LIR(nextLIR);
@@ -40,7 +40,7 @@ static void applyRedundantBranchElimination(CompilationUnit *cUnit)
                 /*
                  * Is the branch target the next instruction?
                  */
-                if (nextLIR == (Armv5teLIR *) thisLIR->generic.target) {
+                if (nextLIR == (ArmLIR *) thisLIR->generic.target) {
                     thisLIR->isNop = true;
                     break;
                 }
@@ -49,7 +49,7 @@ static void applyRedundantBranchElimination(CompilationUnit *cUnit)
                  * Found real useful stuff between the branch and the target
                  */
                 if (!isPseudoOpCode(nextLIR->opCode) ||
-                    nextLIR->opCode == ARMV5TE_PSEUDO_ALIGN4)
+                    nextLIR->opCode == ARM_PSEUDO_ALIGN4)
                     break;
             }
         }

diff --git a/vm/compiler/codegen/armv5te/LocalOptimizations.c b/vm/compiler/codegen/arm/LocalOptimizations.c
similarity index 81%
rename from vm/compiler/codegen/armv5te/LocalOptimizations.c
rename to vm/compiler/codegen/arm/LocalOptimizations.c
index 1ce91af..30b9d86 100644 (file)
--- a/vm/compiler/codegen/armv5te/LocalOptimizations.c
+++ b/vm/compiler/codegen/arm/LocalOptimizations.c
@@ -16,7 +16,7 @@
 
 #include "Dalvik.h"
 #include "vm/compiler/CompilerInternals.h"
-#include "Armv5teLIR.h"
+#include "ArmLIR.h"
 
 /*
  * Perform a pass of top-down walk to
@@ -24,10 +24,10 @@
  * 2) Sink stores to latest possible slot
  */
 static void applyLoadStoreElimination(CompilationUnit *cUnit,
-                                      Armv5teLIR *headLIR,
-                                      Armv5teLIR *tailLIR)
+                                      ArmLIR *headLIR,
+                                      ArmLIR *tailLIR)
 {
-    Armv5teLIR *thisLIR;
+    ArmLIR *thisLIR;
 
     cUnit->optRound++;
     for (thisLIR = headLIR;
@@ -37,11 +37,11 @@ static void applyLoadStoreElimination(CompilationUnit *cUnit,
         if (thisLIR->age >= cUnit->optRound) {
             continue;
         }
-        if (thisLIR->opCode == ARMV5TE_STR_RRI5 &&
+        if (thisLIR->opCode == THUMB_STR_RRI5 &&
             thisLIR->operands[1] == rFP) {
             int dRegId = thisLIR->operands[2];
             int nativeRegId = thisLIR->operands[0];
-            Armv5teLIR *checkLIR;
+            ArmLIR *checkLIR;
             int sinkDistance = 0;
 
             for (checkLIR = NEXT_LIR(thisLIR);
@@ -49,14 +49,14 @@ static void applyLoadStoreElimination(CompilationUnit *cUnit,
                  checkLIR = NEXT_LIR(checkLIR)) {
 
                 /* Check if a Dalvik register load is redundant */
-                if (checkLIR->opCode == ARMV5TE_LDR_RRI5 &&
+                if (checkLIR->opCode == THUMB_LDR_RRI5 &&
                     checkLIR->operands[1] == rFP &&
                     checkLIR->operands[2] == dRegId) {
                     /* Insert a move to replace the load */
                     if (checkLIR->operands[0] != nativeRegId) {
-                        Armv5teLIR *moveLIR =
-                            dvmCompilerNew(sizeof(Armv5teLIR), true);
-                        moveLIR->opCode = ARMV5TE_MOV_RR;
+                        ArmLIR *moveLIR =
+                            dvmCompilerNew(sizeof(ArmLIR), true);
+                        moveLIR->opCode = THUMB_MOV_RR;
                         moveLIR->operands[0] = checkLIR->operands[0];
                         moveLIR->operands[1] = nativeRegId;
                         /*
@@ -70,7 +70,7 @@ static void applyLoadStoreElimination(CompilationUnit *cUnit,
                     continue;
 
                 /* Found a true output dependency - nuke the previous store */
-                } else if (checkLIR->opCode == ARMV5TE_STR_RRI5 &&
+                } else if (checkLIR->opCode == THUMB_STR_RRI5 &&
                            checkLIR->operands[1] == rFP &&
                            checkLIR->operands[2] == dRegId) {
                     thisLIR->isNop = true;
@@ -90,10 +90,10 @@ static void applyLoadStoreElimination(CompilationUnit *cUnit,
                      * Conservatively assume there is a memory dependency
                      * for st/ld multiples and reg+reg address mode
                      */
-                    stopHere |= checkLIR->opCode == ARMV5TE_STMIA ||
-                                checkLIR->opCode == ARMV5TE_LDMIA ||
-                                checkLIR->opCode == ARMV5TE_STR_RRR ||
-                                checkLIR->opCode == ARMV5TE_LDR_RRR;
+                    stopHere |= checkLIR->opCode == THUMB_STMIA ||
+                                checkLIR->opCode == THUMB_LDMIA ||
+                                checkLIR->opCode == THUMB_STR_RRR ||
+                                checkLIR->opCode == THUMB_LDR_RRR;
 
                     stopHere |= (EncodingMap[checkLIR->opCode].flags &
                                  IS_BRANCH) != 0;
@@ -103,8 +103,8 @@ static void applyLoadStoreElimination(CompilationUnit *cUnit,
 
                         /* The store can be sunk for at least one cycle */
                         if (sinkDistance != 0) {
-                            Armv5teLIR *newStoreLIR =
-                                dvmCompilerNew(sizeof(Armv5teLIR), true);
+                            ArmLIR *newStoreLIR =
+                                dvmCompilerNew(sizeof(ArmLIR), true);
                             *newStoreLIR = *thisLIR;
                             newStoreLIR->age = cUnit->optRound;
                             /*
@@ -134,6 +134,6 @@ void dvmCompilerApplyLocalOptimizations(CompilationUnit *cUnit, LIR *headLIR,
                                         LIR *tailLIR)
 {
     applyLoadStoreElimination(cUnit,
-                              (Armv5teLIR *) headLIR,
-                              (Armv5teLIR *) tailLIR);
+                              (ArmLIR *) headLIR,
+                              (ArmLIR *) tailLIR);
 }

diff --git a/vm/compiler/codegen/armv5te/armv5te-vfp/ArchVariant.c b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c
similarity index 97%
rename from vm/compiler/codegen/armv5te/armv5te-vfp/ArchVariant.c
rename to vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c
index 583cf00..6c5b010 100644 (file)
--- a/vm/compiler/codegen/armv5te/armv5te-vfp/ArchVariant.c
+++ b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c
@@ -45,10 +45,10 @@ static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpCode opCode)
      * we fake BLX_1 is a two operand instruction and the absolute target
      * address is stored in operand[1].
      */
-    newLIR2(cUnit, ARMV5TE_BLX_1,
+    newLIR2(cUnit, THUMB_BLX_1,
             (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
             (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
-    newLIR2(cUnit, ARMV5TE_BLX_2,
+    newLIR2(cUnit, THUMB_BLX_2,
             (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
             (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
 #else
@@ -69,7 +69,7 @@ static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpCode opCode)
         default: templatePtr = NULL;
     }
     loadConstant(cUnit, r7, (int) templatePtr);
-    newLIR1(cUnit, ARMV5TE_BLX_R, r7);
+    newLIR1(cUnit, THUMB_BLX_R, r7);
 #endif
 }
 
@@ -119,8 +119,8 @@ static bool genInlineSqrt(CompilationUnit *cUnit, MIR *mir)
     int vSrc = mir->dalvikInsn.vA;
     loadValueAddress(cUnit, vSrc, r2);
     genDispatchToHandler(cUnit, TEMPLATE_SQRT_DOUBLE_VFP);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, r0, rGLUE, offset >> 2);
-    newLIR3(cUnit, ARMV5TE_STR_RRI5, r1, rGLUE, (offset >> 2) + 1);
+    newLIR3(cUnit, THUMB_STR_RRI5, r0, rGLUE, offset >> 2);
+    newLIR3(cUnit, THUMB_STR_RRI5, r1, rGLUE, (offset >> 2) + 1);
     return false;
 }
 

diff --git a/vm/compiler/codegen/armv5te/armv5te-vfp/ArchVariant.h b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.h
similarity index 81%
rename from vm/compiler/codegen/armv5te/armv5te-vfp/ArchVariant.h
rename to vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.h
index c444bc9..9f862e8 100644 (file)
--- a/vm/compiler/codegen/armv5te/armv5te-vfp/ArchVariant.h
+++ b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.h
@@ -14,8 +14,8 @@
  * limitations under the License.
  */
 
-#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_ARMV5TE_VFP_ARCHVARIANT_H
-#define _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_ARMV5TE_VFP_ARCHVARIANT_H
+#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H
+#define _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H
 
 /* Create the TemplateOpcode enum */
 #define JIT_TEMPLATE(X) TEMPLATE_##X,
@@ -31,4 +31,4 @@ typedef enum {
 } TemplateOpCode;
 #undef JIT_TEMPLATE
 
-#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_ARMV5TE_VFP_ARCHVARIANT_H */
+#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H */

diff --git a/vm/compiler/codegen/armv5te/armv5te/ArchVariant.c b/vm/compiler/codegen/arm/armv5te/ArchVariant.c
similarity index 98%
rename from vm/compiler/codegen/armv5te/armv5te/ArchVariant.c
rename to vm/compiler/codegen/arm/armv5te/ArchVariant.c
index d0122c8..a1f2b00 100644 (file)
--- a/vm/compiler/codegen/armv5te/armv5te/ArchVariant.c
+++ b/vm/compiler/codegen/arm/armv5te/ArchVariant.c
@@ -45,10 +45,10 @@ static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpCode opCode)
      * we fake BLX_1 is a two operand instruction and the absolute target
      * address is stored in operand[1].
      */
-    newLIR2(cUnit, ARMV5TE_BLX_1,
+    newLIR2(cUnit, THUMB_BLX_1,
             (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
             (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
-    newLIR2(cUnit, ARMV5TE_BLX_2,
+    newLIR2(cUnit, THUMB_BLX_2,
             (int) gDvmJit.codeCache + templateEntryOffsets[opCode],
             (int) gDvmJit.codeCache + templateEntryOffsets[opCode]);
 #else
@@ -69,7 +69,7 @@ static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpCode opCode)
         default: templatePtr = NULL;
     }
     loadConstant(cUnit, r7, (int) templatePtr);
-    newLIR1(cUnit, ARMV5TE_BLX_R, r7);
+    newLIR1(cUnit, THUMB_BLX_R, r7);
 #endif
 }
 

diff --git a/vm/compiler/codegen/armv5te/armv5te/ArchVariant.h b/vm/compiler/codegen/arm/armv5te/ArchVariant.h
similarity index 81%
rename from vm/compiler/codegen/armv5te/armv5te/ArchVariant.h
rename to vm/compiler/codegen/arm/armv5te/ArchVariant.h
index 23f2483..6420df7 100644 (file)
--- a/vm/compiler/codegen/armv5te/armv5te/ArchVariant.h
+++ b/vm/compiler/codegen/arm/armv5te/ArchVariant.h
@@ -14,8 +14,8 @@
  * limitations under the License.
  */
 
-#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_ARMV5TE_ARCHVARIANT_H
-#define _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_ARMV5TE_ARCHVARIANT_H
+#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_ARCHVARIANT_H
+#define _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_ARCHVARIANT_H
 
 /* Create the TemplateOpcode enum */
 #define JIT_TEMPLATE(X) TEMPLATE_##X,
@@ -31,4 +31,4 @@ typedef enum {
 } TemplateOpCode;
 #undef JIT_TEMPLATE
 
-#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_ARMV5TE_ARCHVARIANT_H */
+#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_ARCHVARIANT_H */

diff --git a/vm/compiler/codegen/armv5te/Armv5teLIR.h b/vm/compiler/codegen/armv5te/Armv5teLIR.h
deleted file mode 100644 (file)
index 6408038..0000000
--- a/vm/compiler/codegen/armv5te/Armv5teLIR.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * Copyright (C) 2009 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "Dalvik.h"
-#include "compiler/CompilerInternals.h"
-
-#ifndef _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_H
-#define _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_H
-
-/*
- * r0, r1, r2, r3, and r7 are always scratch
- * r4PC is scratch if used solely in the compiled land. Otherwise it holds the
- * Dalvik PC.
- * rFP holds the current frame pointer
- * rGLUE holds &InterpState
- */
-typedef enum NativeRegisterPool {
-    r0 = 0,
-    r1 = 1,
-    r2 = 2,
-    r3 = 3,
-    r4PC = 4,
-    rFP = 5,
-    rGLUE = 6,
-    r7 = 7,
-    r8 = 8,
-    r9 = 9,
-    r10 = 10,
-    r11 = 11,
-    r12 = 12,
-    r13 = 13,
-    rlr = 14,
-    rpc = 15
-} NativeRegisterPool;
-
-/* Mask to convert high reg to low for Thumb */
-#define THUMB_REG_MASK 0x7
-
-/* Thumb condition encodings */
-typedef enum Armv5teConditionCode {
-    ARM_COND_EQ = 0x0,    /* 0000 */
-    ARM_COND_NE = 0x1,    /* 0001 */
-    ARM_COND_LT = 0xb,    /* 1011 */
-    ARM_COND_GE = 0xa,    /* 1010 */
-    ARM_COND_GT = 0xc,    /* 1100 */
-    ARM_COND_LE = 0xd,    /* 1101 */
-    ARM_COND_CS = 0x2,    /* 0010 */
-    ARM_COND_MI = 0x4,    /* 0100 */
-} Armv5teConditionCode;
-
-#define isPseudoOpCode(opCode) ((int)(opCode) < 0)
-
-/*
- * The following enum defines the list of supported Thumb instructions by the
- * assembler. Their corresponding snippet positions will be defined in
- * Assemble.c.
- */
-typedef enum Armv5teOpCode {
-    ARMV5TE_PSEUDO_TARGET_LABEL = -11,
-    ARMV5TE_PSEUDO_CHAINING_CELL_HOT = -10,
-    ARMV5TE_PSEUDO_CHAINING_CELL_INVOKE_PREDICTED = -9,
-    ARMV5TE_PSEUDO_CHAINING_CELL_INVOKE_SINGLETON = -8,
-    ARMV5TE_PSEUDO_CHAINING_CELL_NORMAL = -7,
-    ARMV5TE_PSEUDO_DALVIK_BYTECODE_BOUNDARY = -6,
-    ARMV5TE_PSEUDO_ALIGN4 = -5,
-    ARMV5TE_PSEUDO_PC_RECONSTRUCTION_CELL = -4,
-    ARMV5TE_PSEUDO_PC_RECONSTRUCTION_BLOCK_LABEL = -3,
-    ARMV5TE_PSEUDO_EH_BLOCK_LABEL = -2,
-    ARMV5TE_PSEUDO_NORMAL_BLOCK_LABEL = -1,
-    /************************************************************************/
-    ARMV5TE_16BIT_DATA,     /* DATA   [0] rd[15..0] */
-    ARMV5TE_ADC,            /* adc     [0100000101] rm[5..3] rd[2..0] */
-    ARMV5TE_ADD_RRI3,       /* add(1)  [0001110] imm_3[8..6] rn[5..3] rd[2..0]*/
-    ARMV5TE_ADD_RI8,        /* add(2)  [00110] rd[10..8] imm_8[7..0] */
-    ARMV5TE_ADD_RRR,        /* add(3)  [0001100] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_ADD_RR_LH,      /* add(4)  [01000100] H12[01] rm[5..3] rd[2..0] */
-    ARMV5TE_ADD_RR_HL,      /* add(4)  [01001000] H12[10] rm[5..3] rd[2..0] */
-    ARMV5TE_ADD_RR_HH,      /* add(4)  [01001100] H12[11] rm[5..3] rd[2..0] */
-    ARMV5TE_ADD_PC_REL,     /* add(5)  [10100] rd[10..8] imm_8[7..0] */
-    ARMV5TE_ADD_SP_REL,     /* add(6)  [10101] rd[10..8] imm_8[7..0] */
-    ARMV5TE_ADD_SPI7,       /* add(7)  [101100000] imm_7[6..0] */
-    ARMV5TE_AND_RR,         /* and     [0100000000] rm[5..3] rd[2..0] */
-    ARMV5TE_ASR,            /* asr(1)  [00010] imm_5[10..6] rm[5..3] rd[2..0] */
-    ARMV5TE_ASRV,           /* asr(2)  [0100000100] rs[5..3] rd[2..0] */
-    ARMV5TE_B_COND,         /* b(1)    [1101] cond[11..8] offset_8[7..0] */
-    ARMV5TE_B_UNCOND,       /* b(2)    [11100] offset_11[10..0] */
-    ARMV5TE_BIC,            /* bic     [0100001110] rm[5..3] rd[2..0] */
-    ARMV5TE_BKPT,           /* bkpt    [10111110] imm_8[7..0] */
-    ARMV5TE_BLX_1,          /* blx(1)  [111] H[10] offset_11[10..0] */
-    ARMV5TE_BLX_2,          /* blx(1)  [111] H[01] offset_11[10..0] */
-    ARMV5TE_BL_1,           /* blx(1)  [111] H[10] offset_11[10..0] */
-    ARMV5TE_BL_2,           /* blx(1)  [111] H[11] offset_11[10..0] */
-    ARMV5TE_BLX_R,          /* blx(2)  [010001111] H2[6..6] rm[5..3] SBZ[000] */
-    ARMV5TE_BX,             /* bx      [010001110] H2[6..6] rm[5..3] SBZ[000] */
-    ARMV5TE_CMN,            /* cmn     [0100001011] rm[5..3] rd[2..0] */
-    ARMV5TE_CMP_RI8,        /* cmp(1)  [00101] rn[10..8] imm_8[7..0] */
-    ARMV5TE_CMP_RR,         /* cmp(2)  [0100001010] rm[5..3] rd[2..0] */
-    ARMV5TE_CMP_LH,         /* cmp(3)  [01000101] H12[01] rm[5..3] rd[2..0] */
-    ARMV5TE_CMP_HL,         /* cmp(3)  [01000110] H12[10] rm[5..3] rd[2..0] */
-    ARMV5TE_CMP_HH,         /* cmp(3)  [01000111] H12[11] rm[5..3] rd[2..0] */
-    ARMV5TE_EOR,            /* eor     [0100000001] rm[5..3] rd[2..0] */
-    ARMV5TE_LDMIA,          /* ldmia   [11001] rn[10..8] reglist [7..0] */
-    ARMV5TE_LDR_RRI5,       /* ldr(1)  [01101] imm_5[10..6] rn[5..3] rd[2..0] */
-    ARMV5TE_LDR_RRR,        /* ldr(2)  [0101100] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_LDR_PC_REL,     /* ldr(3)  [01001] rd[10..8] imm_8[7..0] */
-    ARMV5TE_LDR_SP_REL,     /* ldr(4)  [10011] rd[10..8] imm_8[7..0] */
-    ARMV5TE_LDRB_RRI5,      /* ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0] */
-    ARMV5TE_LDRB_RRR,       /* ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_LDRH_RRI5,      /* ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0] */
-    ARMV5TE_LDRH_RRR,       /* ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_LDRSB_RRR,      /* ldrsb   [0101011] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_LDRSH_RRR,      /* ldrsh   [0101111] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_LSL,            /* lsl(1)  [00000] imm_5[10..6] rm[5..3] rd[2..0] */
-    ARMV5TE_LSLV,           /* lsl(2)  [0100000010] rs[5..3] rd[2..0] */
-    ARMV5TE_LSR,            /* lsr(1)  [00001] imm_5[10..6] rm[5..3] rd[2..0] */
-    ARMV5TE_LSRV,           /* lsr(2)  [0100000011] rs[5..3] rd[2..0] */
-    ARMV5TE_MOV_IMM,        /* mov(1)  [00100] rd[10..8] imm_8[7..0] */
-    ARMV5TE_MOV_RR,         /* mov(2)  [0001110000] rn[5..3] rd[2..0] */
-    ARMV5TE_MOV_RR_H2H,     /* mov(3)  [01000111] H12[11] rm[5..3] rd[2..0] */
-    ARMV5TE_MOV_RR_H2L,     /* mov(3)  [01000110] H12[01] rm[5..3] rd[2..0] */
-    ARMV5TE_MOV_RR_L2H,     /* mov(3)  [01000101] H12[10] rm[5..3] rd[2..0] */
-    ARMV5TE_MUL,            /* mul     [0100001101] rm[5..3] rd[2..0] */
-    ARMV5TE_MVN,            /* mvn     [0100001111] rm[5..3] rd[2..0] */
-    ARMV5TE_NEG,            /* neg     [0100001001] rm[5..3] rd[2..0] */
-    ARMV5TE_ORR,            /* orr     [0100001100] rm[5..3] rd[2..0] */
-    ARMV5TE_POP,            /* pop     [1011110] r[8..8] rl[7..0] */
-    ARMV5TE_PUSH,           /* push    [1011010] r[8..8] rl[7..0] */
-    ARMV5TE_ROR,            /* ror     [0100000111] rs[5..3] rd[2..0] */
-    ARMV5TE_SBC,            /* sbc     [0100000110] rm[5..3] rd[2..0] */
-    ARMV5TE_STMIA,          /* stmia   [11000] rn[10..8] reglist [7.. 0] */
-    ARMV5TE_STR_RRI5,       /* str(1)  [01100] imm_5[10..6] rn[5..3] rd[2..0] */
-    ARMV5TE_STR_RRR,        /* str(2)  [0101000] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_STR_SP_REL,     /* str(3)  [10010] rd[10..8] imm_8[7..0] */
-    ARMV5TE_STRB_RRI5,      /* strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0] */
-    ARMV5TE_STRB_RRR,       /* strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_STRH_RRI5,      /* strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0] */
-    ARMV5TE_STRH_RRR,       /* strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_SUB_RRI3,       /* sub(1)  [0001111] imm_3[8..6] rn[5..3] rd[2..0]*/
-    ARMV5TE_SUB_RI8,        /* sub(2)  [00111] rd[10..8] imm_8[7..0] */
-    ARMV5TE_SUB_RRR,        /* sub(3)  [0001101] rm[8..6] rn[5..3] rd[2..0] */
-    ARMV5TE_SUB_SPI7,       /* sub(4)  [101100001] imm_7[6..0] */
-    ARMV5TE_SWI,            /* swi     [11011111] imm_8[7..0] */
-    ARMV5TE_TST,            /* tst     [0100001000] rm[5..3] rn[2..0] */
-    ARMV5TE_LAST,
-} Armv5teOpCode;
-
-/* Bit flags describing the behavior of each native opcode */
-typedef enum Armv5teOpFeatureFlags {
-    IS_BRANCH =           1 << 1,
-    CLOBBER_DEST =        1 << 2,
-    CLOBBER_SRC1 =        1 << 3,
-    NO_OPERAND =          1 << 4,
-    IS_UNARY_OP =         1 << 5,
-    IS_BINARY_OP =        1 << 6,
-    IS_TERTIARY_OP =      1 << 7,
-} Armv5teOpFeatureFlags;
-
-/* Struct used to define the snippet positions for each Thumb opcode */
-typedef struct Armv5teEncodingMap {
-    short skeleton;
-    struct {
-        int end;
-        int start;
-    } fieldLoc[3];
-    Armv5teOpCode opCode;
-    int flags;
-    char *name;
-    char* fmt;
-    int size;
-} Armv5teEncodingMap;
-
-extern Armv5teEncodingMap EncodingMap[ARMV5TE_LAST];
-
-/*
- * Each instance of this struct holds a pseudo or real LIR instruction:
- * - pesudo ones (eg labels and marks) and will be discarded by the assembler.
- * - real ones will e assembled into Thumb instructions.
- */
-typedef struct Armv5teLIR {
-    LIR generic;
-    Armv5teOpCode opCode;
-    int operands[3];    // [0..2] = [dest, src1, src2]
-    bool isNop;         // LIR is optimized away
-    int age;            // default is 0, set lazily by the optimizer
-    int size;           // 16-bit unit size (1 for thumb, 1 or 2 for thumb2)
-} Armv5teLIR;
-
-/* Chain cell for predicted method invocation */
-typedef struct PredictedChainingCell {
-    u4 branch;                  /* Branch to chained destination */
-    const ClassObject *clazz;   /* key #1 for prediction */
-    const Method *method;       /* key #2 to lookup native PC from dalvik PC */
-    u4 counter;                 /* counter to patch the chaining cell */
-} PredictedChainingCell;
-
-/* Init values when a predicted chain is initially assembled */
-#define PREDICTED_CHAIN_BX_PAIR_INIT     0
-#define PREDICTED_CHAIN_CLAZZ_INIT       0
-#define PREDICTED_CHAIN_METHOD_INIT      0
-#define PREDICTED_CHAIN_COUNTER_INIT     0
-
-/* Used when the callee is not compiled yet */
-#define PREDICTED_CHAIN_COUNTER_DELAY    16
-
-/* Rechain after this many mis-predictions have happened */
-#define PREDICTED_CHAIN_COUNTER_RECHAIN  1024
-
-/* Used if the resolved callee is a native method */
-#define PREDICTED_CHAIN_COUNTER_AVOID    0x7fffffff
-
-/* Utility macros to traverse the LIR/Armv5teLIR list */
-#define NEXT_LIR(lir) ((Armv5teLIR *) lir->generic.next)
-#define PREV_LIR(lir) ((Armv5teLIR *) lir->generic.prev)
-
-#define NEXT_LIR_LVALUE(lir) (lir)->generic.next
-#define PREV_LIR_LVALUE(lir) (lir)->generic.prev
-
-#define CHAIN_CELL_OFFSET_TAG   0xcdab
-
-#endif /* _DALVIK_VM_COMPILER_CODEGEN_ARMV5TE_H */

diff --git a/vm/compiler/template/armv5te/TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN.S b/vm/compiler/template/armv5te/TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN.S
index dcbadde..9ee49a8 100644 (file)
--- a/vm/compiler/template/armv5te/TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN.S
+++ b/vm/compiler/template/armv5te/TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN.S
@@ -4,7 +4,7 @@
      * Thumb code through the link register to transfer control to the callee
      * method through a dedicated chaining cell.
      *
-     * The predicted chaining cell is declared in Armv5teLIR.h with the
+     * The predicted chaining cell is declared in ArmLIR.h with the
      * following layout:
      *
      *  typedef struct PredictedChainingCell {

diff --git a/vm/compiler/template/out/CompilerTemplateAsm-armv5te-vfp.S b/vm/compiler/template/out/CompilerTemplateAsm-armv5te-vfp.S
index 22d6d78..2c669f8 100644 (file)
--- a/vm/compiler/template/out/CompilerTemplateAsm-armv5te-vfp.S
+++ b/vm/compiler/template/out/CompilerTemplateAsm-armv5te-vfp.S
@@ -325,7 +325,7 @@ dvmCompiler_TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN:
      * Thumb code through the link register to transfer control to the callee
      * method through a dedicated chaining cell.
      *
-     * The predicted chaining cell is declared in Armv5teLIR.h with the
+     * The predicted chaining cell is declared in ArmLIR.h with the
      * following layout:
      *
      *  typedef struct PredictedChainingCell {

diff --git a/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S b/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S
index a9cf2d3..b973691 100644 (file)
--- a/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S
+++ b/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S
@@ -325,7 +325,7 @@ dvmCompiler_TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN:
      * Thumb code through the link register to transfer control to the callee
      * method through a dedicated chaining cell.
      *
-     * The predicted chaining cell is declared in Armv5teLIR.h with the
+     * The predicted chaining cell is declared in ArmLIR.h with the
      * following layout:
      *
      *  typedef struct PredictedChainingCell {

diff --git a/vm/compiler/template/out/CompilerTemplateAsm-armv7-a.S b/vm/compiler/template/out/CompilerTemplateAsm-armv7-a.S
index 57cbba5..1faf7f6 100644 (file)
--- a/vm/compiler/template/out/CompilerTemplateAsm-armv7-a.S
+++ b/vm/compiler/template/out/CompilerTemplateAsm-armv7-a.S
@@ -325,7 +325,7 @@ dvmCompiler_TEMPLATE_INVOKE_METHOD_PREDICTED_CHAIN:
      * Thumb code through the link register to transfer control to the callee
      * method through a dedicated chaining cell.
      *
-     * The predicted chaining cell is declared in Armv5teLIR.h with the
+     * The predicted chaining cell is declared in ArmLIR.h with the
      * following layout:
      *
      *  typedef struct PredictedChainingCell {