[AArch64][SVE] Asm: Data-dependent loop predicate partitioning instructions.

This patch adds support for instructions that partition a predicate
based on data-dependent termination conditions in a loop.

  BRKA      Break after the first true condition
  BRKAS     Break after the first true condition, setting condition flags
  BRKB      Break before the first true condition
  BRKBS     Break before the first true condition, setting condition flags

  BRKPA     Break after the first true condition, propagating from the
            previous partition
  BRKPAS    Break after the first true condition, propagating from the
            previous partition, setting condition flags
  BRKPB     Break before the first true condition, propagating from the
            previous partition
  BRKPBS    Break before the first true condition, propagating from the
            previous partition, setting condition flags

  BRKN      Propagate break to next partition
  BKRNS     Propagate break to next partition, setting condition flags

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338196 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 16e6ddd..c3d916b 100644 (file)
--- a/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -224,6 +224,21 @@ let Predicates = [HasSVE] in {
   def FEXPA_ZZ_S : sve_int_bin_cons_misc_0_c<0b10000000, "fexpa", ZPR32>;
   def FEXPA_ZZ_D : sve_int_bin_cons_misc_0_c<0b11000000, "fexpa", ZPR64>;
 
+  def BRKPA_PPzPP  : sve_int_brkp<0b00, "brkpa">;
+  def BRKPAS_PPzPP : sve_int_brkp<0b10, "brkpas">;
+  def BRKPB_PPzPP  : sve_int_brkp<0b01, "brkpb">;
+  def BRKPBS_PPzPP : sve_int_brkp<0b11, "brkpbs">;
+
+  def BRKN_PPzP    : sve_int_brkn<0b0, "brkn">;
+  def BRKNS_PPzP   : sve_int_brkn<0b1, "brkns">;
+
+  defm BRKA_PPzP  : sve_int_break_z<0b000, "brka">;
+  defm BRKA_PPmP  : sve_int_break_m<0b001, "brka">;
+  defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas">;
+  defm BRKB_PPzP  : sve_int_break_z<0b100, "brkb">;
+  defm BRKB_PPmP  : sve_int_break_m<0b101, "brkb">;
+  defm BRKBS_PPzP : sve_int_break_z<0b110, "brkbs">;
+
   def AND_PPzPP   : sve_int_pred_log<0b0000, "and">;
   def BIC_PPzPP   : sve_int_pred_log<0b0001, "bic">;
   def EOR_PPzPP   : sve_int_pred_log<0b0010, "eor">;

diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td
index 17b3f60..85396f5 100644 (file)
--- a/lib/Target/AArch64/SVEInstrFormats.td
+++ b/lib/Target/AArch64/SVEInstrFormats.td
@@ -4117,3 +4117,88 @@ multiclass sve_int_reduce_2<bits<3> opc, string asm> {
   def _S : sve_int_reduce<0b10, 0b11, opc, asm, ZPR32, FPR32>;
   def _D : sve_int_reduce<0b11, 0b11, opc, asm, ZPR64, FPR64>;
 }
+
+
+//===----------------------------------------------------------------------===//
+// SVE Propagate Break Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_brkp<bits<2> opc, string asm>
+: I<(outs PPR8:$Pd), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$Pm),
+  asm, "\t$Pd, $Pg/z, $Pn, $Pm",
+  "",
+  []>, Sched<[]> {
+  bits<4> Pd;
+  bits<4> Pg;
+  bits<4> Pm;
+  bits<4> Pn;
+  let Inst{31-24} = 0b00100101;
+  let Inst{23}    = 0b0;
+  let Inst{22}    = opc{1};
+  let Inst{21-20} = 0b00;
+  let Inst{19-16} = Pm;
+  let Inst{15-14} = 0b11;
+  let Inst{13-10} = Pg;
+  let Inst{9}     = 0b0;
+  let Inst{8-5}   = Pn;
+  let Inst{4}     = opc{0};
+  let Inst{3-0}   = Pd;
+
+  let Defs = !if(!eq (opc{1}, 1), [NZCV], []);
+}
+
+
+//===----------------------------------------------------------------------===//
+// SVE Partition Break Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_brkn<bit S, string asm>
+: I<(outs PPR8:$Pdm), (ins PPRAny:$Pg, PPR8:$Pn, PPR8:$_Pdm),
+  asm, "\t$Pdm, $Pg/z, $Pn, $_Pdm",
+  "",
+  []>, Sched<[]> {
+  bits<4> Pdm;
+  bits<4> Pg;
+  bits<4> Pn;
+  let Inst{31-23} = 0b001001010;
+  let Inst{22}    = S;
+  let Inst{21-14} = 0b01100001;
+  let Inst{13-10} = Pg;
+  let Inst{9}     = 0b0;
+  let Inst{8-5}   = Pn;
+  let Inst{4}     = 0b0;
+  let Inst{3-0}   = Pdm;
+
+  let Constraints = "$Pdm = $_Pdm";
+  let Defs = !if(!eq (S, 0b1), [NZCV], []);
+}
+
+class sve_int_break<bits<3> opc, string asm, string suffix, dag iops>
+: I<(outs PPR8:$Pd), iops,
+  asm, "\t$Pd, $Pg"#suffix#", $Pn",
+  "",
+  []>, Sched<[]> {
+  bits<4> Pd;
+  bits<4> Pg;
+  bits<4> Pn;
+  let Inst{31-24} = 0b00100101;
+  let Inst{23-22} = opc{2-1};
+  let Inst{21-14} = 0b01000001;
+  let Inst{13-10} = Pg;
+  let Inst{9}     = 0b0;
+  let Inst{8-5}   = Pn;
+  let Inst{4}     = opc{0};
+  let Inst{3-0}   = Pd;
+
+  let Constraints = !if(!eq (opc{0}, 1), "$Pd = $_Pd", "");
+  let Defs = !if(!eq (opc{1}, 1), [NZCV], []);
+
+}
+
+multiclass sve_int_break_m<bits<3> opc, string asm> {
+  def NAME : sve_int_break<opc, asm, "/m", (ins PPR8:$_Pd, PPRAny:$Pg, PPR8:$Pn)>;
+}
+
+multiclass sve_int_break_z<bits<3> opc, string asm> {
+  def NAME : sve_int_break<opc, asm, "/z", (ins PPRAny:$Pg, PPR8:$Pn)>;
+}

diff --git a/test/MC/AArch64/SVE/brka-diagnostics.s b/test/MC/AArch64/SVE/brka-diagnostics.s
new file mode 100644 (file)
index 0000000..140ac00
--- /dev/null
+++ b/test/MC/AArch64/SVE/brka-diagnostics.s
@@ -0,0 +1,10 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Only .b is supported
+
+brka  p0.s, p15/z, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brka  p0.s, p15/z, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brka.s b/test/MC/AArch64/SVE/brka.s
new file mode 100644 (file)
index 0000000..d87e763
--- /dev/null
+++ b/test/MC/AArch64/SVE/brka.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brka  p0.b, p15/m, p15.b
+// CHECK-INST: brka    p0.b, p15/m, p15.b
+// CHECK-ENCODING: [0xf0,0x7d,0x10,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: f0 7d 10 25 <unknown>
+
+brka  p0.b, p15/z, p15.b
+// CHECK-INST: brka    p0.b, p15/z, p15.b
+// CHECK-ENCODING: [0xe0,0x7d,0x10,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 7d 10 25 <unknown>

diff --git a/test/MC/AArch64/SVE/brkas-diagnostics.s b/test/MC/AArch64/SVE/brkas-diagnostics.s
new file mode 100644 (file)
index 0000000..14fe7cf
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkas-diagnostics.s
@@ -0,0 +1,19 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Only .b is supported
+
+brkas  p0.s, p15/z, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brkas  p0.s, p15/z, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// flag-setting variant does not have merging predication
+
+brkas  p0.b, p15/m, p15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: brkas  p0.b, p15/m, p15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brkas.s b/test/MC/AArch64/SVE/brkas.s
new file mode 100644 (file)
index 0000000..f75c5bc
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkas.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brkas  p0.b, p15/z, p15.b
+// CHECK-INST: brkas   p0.b, p15/z, p15.b
+// CHECK-ENCODING: [0xe0,0x7d,0x50,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 7d 50 25 <unknown>

diff --git a/test/MC/AArch64/SVE/brkb-diagnostics.s b/test/MC/AArch64/SVE/brkb-diagnostics.s
new file mode 100644 (file)
index 0000000..7f87f15
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkb-diagnostics.s
@@ -0,0 +1,10 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Only .b is supported
+
+brkb  p0.s, p15/z, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brkb  p0.s, p15/z, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brkb.s b/test/MC/AArch64/SVE/brkb.s
new file mode 100644 (file)
index 0000000..393d294
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkb.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brkb  p0.b, p15/m, p15.b
+// CHECK-INST: brkb    p0.b, p15/m, p15.b
+// CHECK-ENCODING: [0xf0,0x7d,0x90,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: f0 7d 90 25 <unknown>
+
+brkb  p0.b, p15/z, p15.b
+// CHECK-INST: brkb    p0.b, p15/z, p15.b
+// CHECK-ENCODING: [0xe0,0x7d,0x90,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 7d 90 25 <unknown>

diff --git a/test/MC/AArch64/SVE/brkbs-diagnostics.s b/test/MC/AArch64/SVE/brkbs-diagnostics.s
new file mode 100644 (file)
index 0000000..bcb9a64
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkbs-diagnostics.s
@@ -0,0 +1,19 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Only .b is supported
+
+brkbs  p0.s, p15/z, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brkbs  p0.s, p15/z, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// flag-setting variant does not have merging predication
+
+brkbs  p0.b, p15/m, p15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: brkbs  p0.b, p15/m, p15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brkbs.s b/test/MC/AArch64/SVE/brkbs.s
new file mode 100644 (file)
index 0000000..708ec91
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkbs.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brkbs  p0.b, p15/z, p15.b
+// CHECK-INST: brkbs   p0.b, p15/z, p15.b
+// CHECK-ENCODING: [0xe0,0x7d,0xd0,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 7d d0 25 <unknown>

diff --git a/test/MC/AArch64/SVE/brkn-diagnostics.s b/test/MC/AArch64/SVE/brkn-diagnostics.s
new file mode 100644 (file)
index 0000000..87587fb
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkn-diagnostics.s
@@ -0,0 +1,28 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// BRKN only supports merging predication
+
+brkn  p0.b, p15/m, p1.b, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: brkn  p0.b, p15/m, p1.b, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Check tied operand constraints
+
+brkn  p0.b, p15/z, p1.b, p1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: brkn  p0.b, p15/z, p1.b, p1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Only .b is supported
+
+brkn  p15.s, p15/z, p15.s, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brkn  p15.s, p15/z, p15.s, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brkn.s b/test/MC/AArch64/SVE/brkn.s
new file mode 100644 (file)
index 0000000..8494e54
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkn.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brkn  p0.b, p15/z, p1.b, p0.b
+// CHECK-INST: brkn    p0.b, p15/z, p1.b, p0.b
+// CHECK-ENCODING: [0x20,0x7c,0x18,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 7c 18 25 <unknown>
+
+brkn  p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: brkn    p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x18,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 18 25 <unknown>

diff --git a/test/MC/AArch64/SVE/brkns-diagnostics.s b/test/MC/AArch64/SVE/brkns-diagnostics.s
new file mode 100644 (file)
index 0000000..c22d4cd
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkns-diagnostics.s
@@ -0,0 +1,28 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// BRKN only supports merging predication
+
+brkns  p0.b, p15/m, p1.b, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: brkns  p0.b, p15/m, p1.b, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Check tied operand constraints
+
+brkns  p0.b, p15/z, p1.b, p1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: brkns  p0.b, p15/z, p1.b, p1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Only .b is supported
+
+brkns  p15.s, p15/z, p15.s, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brkns  p15.s, p15/z, p15.s, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brkns.s b/test/MC/AArch64/SVE/brkns.s
new file mode 100644 (file)
index 0000000..6fd47f6
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkns.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brkns  p0.b, p15/z, p1.b, p0.b
+// CHECK-INST: brkns   p0.b, p15/z, p1.b, p0.b
+// CHECK-ENCODING: [0x20,0x7c,0x58,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 7c 58 25 <unknown>
+
+brkns  p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: brkns   p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0x7d,0x58,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef 7d 58 25 <unknown>

diff --git a/test/MC/AArch64/SVE/brkpa-diagnostics.s b/test/MC/AArch64/SVE/brkpa-diagnostics.s
new file mode 100644 (file)
index 0000000..d7693c6
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkpa-diagnostics.s
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+brkpa  p15.b, p15/m, p15.b, p15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: brkpa  p15.b, p15/m, p15.b, p15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+brkpa  p15.s, p15/z, p15.s, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brkpa  p15.s, p15/z, p15.s, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brkpa.s b/test/MC/AArch64/SVE/brkpa.s
new file mode 100644 (file)
index 0000000..c283ee2
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkpa.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brkpa  p0.b,  p15/z, p1.b,  p2.b
+// CHECK-INST: brkpa   p0.b, p15/z, p1.b, p2.b
+// CHECK-ENCODING: [0x20,0xfc,0x02,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fc 02 25 <unknown>
+
+brkpa  p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: brkpa   p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0xfd,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef fd 0f 25 <unknown>

diff --git a/test/MC/AArch64/SVE/brkpas-diagnostics.s b/test/MC/AArch64/SVE/brkpas-diagnostics.s
new file mode 100644 (file)
index 0000000..a88e110
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkpas-diagnostics.s
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+brkpas p15.b, p15/m, p15.b, p15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: brkpas p15.b, p15/m, p15.b, p15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+brkpas p15.s, p15/z, p15.s, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brkpas p15.s, p15/z, p15.s, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brkpas.s b/test/MC/AArch64/SVE/brkpas.s
new file mode 100644 (file)
index 0000000..81d5900
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkpas.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brkpas  p0.b,  p15/z, p1.b,  p2.b
+// CHECK-INST: brkpas  p0.b, p15/z, p1.b, p2.b
+// CHECK-ENCODING: [0x20,0xfc,0x42,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 fc 42 25 <unknown>
+
+brkpas  p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: brkpas  p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xef,0xfd,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef fd 4f 25 <unknown>

diff --git a/test/MC/AArch64/SVE/brkpb-diagnostics.s b/test/MC/AArch64/SVE/brkpb-diagnostics.s
new file mode 100644 (file)
index 0000000..e03f0bf
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkpb-diagnostics.s
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+brkpb  p15.b, p15/m, p15.b, p15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: brkpb  p15.b, p15/m, p15.b, p15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+brkpb  p15.s, p15/z, p15.s, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brkpb  p15.s, p15/z, p15.s, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brkpb.s b/test/MC/AArch64/SVE/brkpb.s
new file mode 100644 (file)
index 0000000..039e71f
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkpb.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brkpb  p0.b,  p15/z, p1.b,  p2.b
+// CHECK-INST: brkpb   p0.b, p15/z, p1.b, p2.b
+// CHECK-ENCODING: [0x30,0xfc,0x02,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 fc 02 25 <unknown>
+
+brkpb  p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: brkpb   p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0xfd,0x0f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff fd 0f 25 <unknown>

diff --git a/test/MC/AArch64/SVE/brkpbs-diagnostics.s b/test/MC/AArch64/SVE/brkpbs-diagnostics.s
new file mode 100644 (file)
index 0000000..25e230e
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkpbs-diagnostics.s
@@ -0,0 +1,11 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+brkpbs p15.b, p15/m, p15.b, p15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: brkpbs p15.b, p15/m, p15.b, p15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+brkpbs p15.s, p15/z, p15.s, p15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: brkpbs p15.s, p15/z, p15.s, p15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/test/MC/AArch64/SVE/brkpbs.s b/test/MC/AArch64/SVE/brkpbs.s
new file mode 100644 (file)
index 0000000..1d44178
--- /dev/null
+++ b/test/MC/AArch64/SVE/brkpbs.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+brkpbs  p0.b,  p15/z, p1.b,  p2.b
+// CHECK-INST: brkpbs  p0.b, p15/z, p1.b, p2.b
+// CHECK-ENCODING: [0x30,0xfc,0x42,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 30 fc 42 25 <unknown>
+
+brkpbs  p15.b, p15/z, p15.b, p15.b
+// CHECK-INST: brkpbs  p15.b, p15/z, p15.b, p15.b
+// CHECK-ENCODING: [0xff,0xfd,0x4f,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff fd 4f 25 <unknown>